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high efficiency integrated power solution for multicell lithium ion applications data sheet adp5080 f eatures wide input voltage range: 4 .0 v to 1 5 v high efficiency architecture up to 2 mhz switching frequency 6 s ynchronous rectification dc - to - dc converters channel 1 buck regulator : 3 a maximum channel 2 buck regulator : 1. 15 a maximum channel 3 buck regu lator : 1.5 a maximum channel 4 buck regulator : 0.8 a maximum channel 5 buck regulator : 2 a maximum channel 6 configurable buck or buck boost regulator 2 a maximum for buck regulator configuration 1. 5 a maximum for buck boost regulator configuration chann el 7 high voltage, high performance ldo regulator : 3 0 ma maximum 2 low quiescent current k eep - a live ldo regulator s ldo1 regulator : 4 0 0 ma maximum ldo2 regulator : 300 ma maximum control c ircuit charge p ump for i nternal s witching d river p ower s upply i 2 c - prog rammable output levels and power sequencing package : 72 - ball, 4.5 mm 4.0 mm 0.6 mm wlcsp (0.5 mm pitch) applications dslr cameras non - r eflex (mirrorless) c ameras portable instrumentation f unctional block diagram figure 1 . general description the adp5080 is a fully integrated , high effi ciency power solution for multi cell lithium ion battery applications. the device can connect directly to the battery , which e li minate s the need for pre regulators and , therefore , increase s the battery life of the system . the adp5080 integrates two k eep - a live ldo regulator s , five synchronous buck regulators , a configurab le four - switch buck boost regulator, and a high voltage ldo regulator . the adp5080 is a h ighly integrated power solution that incorporat es all power mosfets, feedback loop compensation , voltage s etting resistor dividers , and discharge switches, as well as a charge pump to gener ate a global bootstrap voltage. all these features help to minimize the number of external components and pcb space required, providing significant advantages for portable a pplications . the switching frequency is selectable on each channel from 750 khz to 2 mhz . key functions for power application s, such as soft start, selectable preset output voltage , and flexible power - up and power - down sequences , are provided on chip and are programmable via the i 2 c interface with fused factory defaults. the adp5080 is available in a 72 - ball wlcsp 0.5 mm pitch package. ldo1 ldo2 i 2 c interface control logic oscillator voltage reference scl sda enable 3v to 3.3v, 300ma 1.0v to 3.3v, 1.15a ch1 buck regulator 0.80v to 1.20v, 3a 5.0v to 5.5v, 400ma charge pump 1.2v to 1.8v/adj, 1.5a 1.8v to 3.55v/adj, 0.8a 3.0v to 5.0v, 2a 3.5v to 5.5v/adj buck only: 2a buck boost: 1.5a 5v to 12v, 30ma 11639-001 fault 4v to 15v 4v to 15v 5v to 25v 4v to 15v 4v to 15v 4v to 15v 4v to 15v 4v to 15v ch 3 buck regulator ch2 buck regulator ch 4 buck regulator ch 6 buck boost regulator ch 5 buck regulator ch7 ldo regulator rev. a document feedba ck information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. sp ecifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p .o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013C 2014 analog devices, inc. all rights reserved. technical support www.analog.com
adp5080 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 housekeeping block specifications ........................................... 4 dc - to - dc converter block specifications .............................. 5 linear regulator block specifications ....................................... 7 i 2 c interface timing specifications ........................................... 8 absolute maximum ratings ............................................................ 9 thermal resistance ...................................................................... 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 typical performance characteristics ........................................... 12 application circuit ......................................................................... 18 theory of operation ...................................................................... 19 uvlo and por .......................................................................... 19 discharge switch ........................................................................ 19 keep - alive ldo regulators ..................................................... 19 dc - to - dc converter channels ............................................... 22 light load and other modes of operation for the dc - to - dc converter channels .................................. 27 switching clock .......................................................................... 28 soft start function ..................................................................... 29 channel 7: high voltage ldo regulator ............................... 29 charge pump .............................................................................. 29 enabling and disabling the output channels ........................ 30 power - good function ............................................................... 31 fault function ............................................................................. 31 undervoltage protection (uvp) .............................................. 32 overvoltage protection (ovp) ................................................. 33 applications information .............................................................. 34 component selection for the buck and buck boost regulators .................................................................................... 34 component selection for the ldo regulators ...................... 36 pcb layout recommendations ............................................... 36 thermal consider ations ............................................................ 37 i 2 c interface .................................................................................... 38 sda and scl pins ...................................................................... 38 i 2 c address .................................................................................. 38 self - clearing register bits ......................................................... 38 i 2 c interface timing diagrams ................................................ 38 co ntrol register information ....................................................... 40 control register map ................................................................ 40 control register details ............................................................ 41 factory default options ................................................................ 61 outline dimensions ....................................................................... 63 ordering guide .......................................................................... 63 revision history 4 /14 revision a : initial version rev. a | page 2 of 64
data sheet adp5080 specifications t j = 25c, v vb att = 7.2 v, v v reg1 = v vdr x = 5 v, v v reg2 = v vddio = 3.3 v, unless otherwise noted. table 1. parameter symbol min typ max unit test conditions/comments inp ut supply voltage range vbat t v v b at t 4. 0 15 v applies to pvin1, pvin2, pvin3, pvin4, pvin5, and pvin6 vildo7 v vildo7 5 25 v vddio v vddio 1.6 3.6 v quiescent current operating quiescent current i q ( vin) 8 11 ma all channels on , nonswi tching vddio i q ( vddio_op) 0.2 a v vddio = v scl = v sda = 3.3 v standby current i q ( v bat t _stnby 1 ) 12 20 a includes ldo1 and ldo2, en low i q ( v bat t _stnby 2 ) 1.25 m a a ll channels off , en high , sel_fsw = 1, freq_cp = 01 u ndervoltage lockout uvlo uvlo rising threshold v uvlo ( r ) 3.45 3.7 3. 85 v at pvin 1 uvlo falling threshold v uvlo ( f ) 3.45 3.55 v a t pvin 1 vbatt uvlo threshold v uvlo ( bat t ) 3.3 v at vbatt, falling reset threshold v uvlo ( por ) 2.4 v at vreg 2 , falling oscillator circuit switching frequency f sw 1.98 2.0 2.02 mhz r osc = 100 k , sel_fsw = 0 1.48 1.5 1.52 mhz r osc = 100 k , sel_fsw = 1 sync pin , input clock frequency range f sync 0.5 2.0 mhz r osc = 100 k min imum on pulse width t sync_ min_on 100 ns m inimum off pulse width t sync_ min_off 100 n s high logic v h ( s ync) 0.8 v vreg2 v v vreg2 = 3.3 v, ?25 c t j +85 c low logic v l ( sync) 0.3 v vreg2 v v vreg2 = 3.3 v, ?25 c t j +85 c logic inputs en pin high level threshold v ih ( en) 2.15 v v vreg2 = 3.3 v, ?25 c t j +85 c low level thresh old v il ( en) 1.45 v v vreg2 = 3.3 v, ?25 c t j +85 c en 34 pin high level threshold v ih ( en 34) 1.25 v v vreg2 = 3.3 v, ?25 c t j +85 c low level threshold v il ( en 34) 0.70 v v vreg2 = 3.3 v, ?25 c t j +85 c scl and sda pins high level threshold v ih ( i2c) 0.7 5 v vddio v v vddio = 3.3 v , ?25 c t j +85 c low level threshold v il ( i2c) 0.3 v vddio v v vddio = 3.3 v , ?25 c t j +85 c logic outputs sda pin low level output voltage v ol ( sda) 0.4 v 3.0 ma sink cu rrent, ?25c t j + 85 c leakage current i leak ( sda) 10 na v sda = 3.3 v clko pin high level output voltage v o h ( clko ) v vreg2 ? 0.4 v 3.0 ma sink current, ?25c t j +85c low level output voltage v ol ( clko ) 0.4 v 3.0 ma sink current, ?25 c t j + 85 c fault p in low level output voltage v ol ( fault ) 0.4 v 3.0 ma source current , ?25c t j +85c leakage current i leak ( fault ) 10 na v fault = 3.3 v rev. a | page 3 of 64
adp5080 data sheet parameter symbol min typ max unit test conditions/comments power g ood rising threshold v pgood ( r) 83 % measured at v out falling threshold v pgood ( f) 79 % measured at v out o vervoltage / undervoltage ovp t hreshold v ovp 125 137 % measured at v out uvp t hreshold v uvp 48 65 % measured at v out thermal shut down tsd rising threshold t tsd 165 c hysteresis t tsd_hys 15 c housekeeping block s pecifications t j = 25c, v vb att = 7.2 v, v v reg1 = v vdr x = 5 v, v v reg2 = v vddio = 3.3 v, unless otherwise noted. table 2. parameter s ymbol min typ max unit test conditions/comments ldo 1 output voltage ( vreg1 pin) fixed voltage range, 1 bit v vreg1 5.0 5.5 v v v bat t = v vreg1 + 0.5 v , i vreg1 = 1 0 ma voltage accuracy v vreg1 ( default) ? 2 + 2 % v v bat t = v vreg1 + 0.5 v , i vreg1 = 1 0 ma load regulation ? v vreg1 /i vreg1 3.5 %/a i vreg1 = 4 ma to 95 ma line regulation ? v vreg1 / v v bat t 0.03 %/v v v bat t = ( v vreg1 + 0.5 v) to 15 v current - limit threshold i ldo1_ ilim 390 550 ma v vreg 1 = 90% of nominal dropout voltage 0.15 v i vreg1 = 10 0 ma , v vreg1 = 5 v input select switch on resistance r ds on_visw1 795 m v visw1 = 5 v c out discharge switch on resistance r dis _ldo1 1 k v vreg1 = 1 v ldo 2 output voltage ( vreg2 pin) fixed voltage range, 2 bits v vreg 2 3.0 3.3 v i vre g2 = 1 0 ma voltage accuracy v vreg 2 ( default) ? 2 + 2 % i vreg2 = 1 0 ma load regulation ? v vreg 2 /i vreg 2 5.5 %/a i vreg2 = 4 ma to 95 ma current - limit threshold i ldo 2 _ ilim 290 400 ma v vreg2 = 90% of nominal input select switch on resistance r dso n _visw 2 1409 m v visw2 = 3.3 v c out discharge switch on resistance r dis _ldo 2 12 v vreg2 = 1 v charge pump c+ switch o n resistance low - side r dson_c+sw1 1. 1 source, pvincp to c+ high - side r dson_c+sw 2 1.0 sink, c+ to bstcp c? switch o n r esistance high - side r dson_c ? sw1 1.0 source, vdr5 to c ? low - side r dson_c ? sw2 785 m sink, c ? to pgnd 5 shunt switch o n resistance r dson_cp 3.3 bstcp to pvincp, en low charge pump start - up threshold cp start 4.0 v at vbat t rev. a | page 4 of 64
data sheet adp5080 dc -to - dc conv erter block specific ations t j = 25c, v vb att = 7.2 v, v v reg1 = v vdr x = 5 v, v v reg2 = v vddio = 3.3 v, unless otherwise noted. table 3. parameter symbol min typ max unit test conditions/comments channel 1 sync buck regulator channel 1 output voltage (fb 1 pin) fixed voltage range, 5 bits v fb 1 0.89 1.20 v reduce_vout1 = 0 0.80 1.11 v reduce_vout1 = 1 feedback voltage accuracy at default vid code v fb 1 ( default) ? 0.8 + 0.8 % ? 1.3 +1. 3 % ?25 c t j +85 c load regulation ?v fb 1 /i load 1 0.15 %/a i load1 = 20 ma to 2 a, auto - psm1 = 0 line regulation ? v fb 1 /v pvin 1 0.004 %/v v pvin 1 = 5 v to 15 v , i load = 1 a sw 1a pin high - side power fet on resistance r ds on _1a h 250 m i d = 100 ma low - side power fet on resistance r dson _1a l 130 m i d = 100 ma sw 1b pin high - side power fet on resistance r dson _1 b h 175 m i d = 100 ma , gate_scal 1 = 0 low - side power fet on resistance r dson _1 b l 95 m i d = 100 ma sw 1 a and sw 1 b pins switch current limit i cl 1 3.1 4.0 a valley current, ?25c t j +85c minimum o ff t ime t off1 ( min) 115 ns minimum d uty c ycle d min1 0 % soft start time t ss1 4 m s ss1 = 10 c out discharge switch on resistance r dis 1 125 v fb1 = 1 v channel 2 sync buck regulator channel 2 output voltage (fb 2 pin) fixed voltage range, 4 bits v fb 2 1.0 3.3 v feedback voltage accuracy at default vid code v fb 2 ( default) ? 0.8 + 0.8 % ? 1.3 + 1.3 % ?25c t j +85 c load regulation ?v fb 2 /i load 2 0.25 %/a i load 2 = 10 ma to 1.0 a, auto - psm2 = 0 line regulation ?v fb 2 /v pvin 2 0.004 %/v v pvin 2 = 5 v to 15 v , i load 2 = 500 m a sw 2 pins high - side power fet on resistance r dson _2 h 235 m i d = 100 ma low - side power fet on resistance r dson _2 l 165 m i d = 100 ma switch current limit i cl 2 1.2 1.8 a valley current, ?25c t j +85 c minimum o ff t ime t off 2 ( min) 100 ns minimum d uty c ycle d min 2 0 % soft start time t ss2 4 m s ss2 = 10 c out discharge switch on resistance r dis 2 125 v fb 2 = 1 v channel 3 sync buck regulator channel 3 output voltage (fb 3 pin) fixed voltage range, 3 bits v fb 3 1.2 1.8 v minimum adjustable voltage 0.8 v vid3 = 111 feedback voltage accuracy at default vid c ode v fb 3 ( default) ? 0.8 + 0.8 % ? 1.3 + 1.3 % ?25c t j +85 c load regulation ?v fb 3 /i load 3 0.17 %/a i load 3 = 15 ma to 1.5 a , auto - psm3 = 0 line regulation ?v fb 3 /v pvin 3 0.003 %/v v pvin 3 = 5 v to 15 v , i load 3 = 700 m a rev. a | page 5 of 64
adp5080 data sheet parameter symbol min typ max unit test conditions/comments sw 3 pins high - side power fet on resistance r ds on _3 h 155 m i d = 100 ma low - side power fet on resistance r ds on _3 l 100 m i d = 100 ma switch current limit i cl 3 2.05 2.8 a valley current, ?25c t j +85 c minimum o ff t ime t off 3 ( min) 90 ns minimum d uty c ycle d min 3 0 % soft start time t ss3 4 m s ss3 = 10 c out discharge switch on resistance r dis 3 125 v fb 3 = 1 v channel 4 sync buck regulator channel 4 output voltage (fb 4 pin) fixed voltage range, 3 bits v fb 4 1.8 3.55 v minimum adjustable vo ltage 0.8 v vid 4 = 111 feedback voltage accuracy at default vid code v fb 4 ( default) ? 1 + 1 % ? 2 + 2 % ?25c t j +85 c load regulation ?v fb 4 /i load 4 0.10 %/a i load 4 = 10 ma to 800 ma, auto - psm4 = 0 line regulation ?v fb 4 /v pvin 4 0.003 %/v v p vin 4 = 5 v to 15 v , i load 4 = 400 m a sw 4 pin high - side power fet on resistance r ds on _4 h 350 m i d = 100 ma low - side power fet on resistance r dson _4 l 345 m i d = 100 ma switch current limit i cl 4 0.96 1.4 a peak current, ?25c t j +85c min imum on time t on4 ( min) 75 ns maximum d uty c ycle d max4 100 % soft start time t ss4 4 m s ss 4 = 10 c out discharge switch on resistance r dis 4 125 v fb 4 = 1 v channel 5 sync buck regulator channel 5 output voltage (fb 5 pin) fixed vo ltage range, 3 bits v fb 5 3.0 5.0 v feedback voltage accuracy at default vid code v fb 5 ( default) ? 1 + 1 % ? 2 + 2 % ?25c t j +85 c load regulation ?v fb 5 /i load 5 0. 05 %/a i load 5 = 20 ma to 2 a, auto - psm5 = 0 line regulation ?v fb 5 /v pvin 5 0.001 %/v v pvin 5 = 5 v to 15 v , i load 5 = 1 a sw 5 pins high - side power fet on resistance r ds on _5 h 200 m i d = 100 ma low - side power fet on resistance r dson _5 l 120 m i d = 100 ma switch current limit i cl 5 2.4 3 a peak current, ?25c t j +85c minimum on time t on5 ( min) 75 ns maximum d uty c ycle d max5 100 % soft start time t ss5 4 m s ss5 = 10 c out discharge switch on resistance r dis 5 125 v fb 5 = 1 v channel 6 buck boost regulator channel 6 output voltage (fb6 pin) fix ed voltage range, 4 bits v fb6 3.5 5.5 v minimum adjustable voltage 0.8 v vid 6 = 1111 accuracy at default vid code v vo ut 6 ( defau lt ) ?1 +1 % ? 2 + 2 % ?25c t j +85 c load regulation ?v vout 6 /i load 6 0.05 %/a b uck b oost configuration , i load 6 = 15 ma to 1.5 a , auto - psm6 = 0 line regulation ?v vout 6 / v pvin 6 0.001 %/v v pvin 6 = 5 v to 15 v , i load 6 = 700 m a rev. a | page 6 of 64
data sheet adp5080 parameter symbol min typ max unit test conditions/comments sw 6a pins low - side power fet on resistance r ds on _6 a l 95 m i d = 100 ma, v vdr6 = 5 v high - side power fet on resistance r dson _6 a h 60 m i d = 100 ma, v vdr6 = 5 v high - side switch current limit i c l 6a 3.2 4.4 a peak current, ?25c t j +85c minimum on time t on6 ( min) 80 ns sw6a high - side on time sw 6b pins low - side power fet on resistance r dson _6 b l 50 m i d = 100 ma hig h - side power fet on resistance r ds on _6 b h 55 m i d = 100 ma boost minimum duty cycle d min6b 0 % sw6b l ow -s ide d uty cycle soft start time t ss6 4 m s ss6 = 10 c out discharge switch on resistance r dis 6 110 v vo ut6 = 1 v linear regulator blo ck spec ifications t j = 25c, v vb att = 7.2 v, v v reg1 = v vdr x = 5 v, v v reg2 = v vddio = 3.3 v, unless otherwise noted. table 4. parameter symbol min typ max unit test conditions/comments channel 7 ldo regulator channel 7 output volta ge v voldo7 5 12 v v vildo7 = v voldo7 + 0.5 v voltage accuracy v voldo7 ( default) ?1 .5 +1 .5 % v vildo7 = v voldo7 + 0.5 v , i load7 = 1 ma ? 2.5 + 2.5 % v vildo7 = v voldo7 + 0.5 v , i load7 = 1 ma, ?2 5 c t j +85 c load regulation ?v voldo7 /i load 7 0.005 %/ m a v vildo7 = v voldo7 + 0.5 v , i load7 = 1 ma to 20 ma line regulation ?v voldo7 /v vi ldo7 0.007 %/v v vildo7 = ( v voldo7 + 0.5 v) to 2 5 v , i load7 = 1 ma dropout voltage 1 v drop 75 mv v voldo7 programmed to 12 v , i voldo7 = 10 ma current limit i cl 7 30 50 ma v voldo7 = 9 5 % of nominal soft start time t ss7 4 m s ss7 = 1 c out discharge sw itch on resistance r di s7 1 k v voldo7 = 1 v 1 dropout voltage is defined as the input - to - output voltage differential when the input voltage is set to the nominal output voltage. rev. a | page 7 of 64
adp5080 data sheet i 2 c interface timing s pe c i fi c ations t j = 25c, v vb att = 7.2 v, v vdr x = 5 v, v vreg2 = v vdd io = 3.3 v, unless otherwise noted. table 5. parameter min typ max unit description f scl 400 khz scl clock frequency t high 0.6 s scl high time t low 1.3 s scl low time t su,dat 100 ns data setup time t hd,dat 0 0.9 s data hold time 1 t su,sta 0.6 s setup time for repeated start t hd,sta 0.6 s hold time for start or repeated start t buf 1.3 s bus free time between a stop condition and a start condition t su,sto 0.6 s setup time for a stop condition t r 20 + 0 .1 c b 2 300 ns rise time of scl and sda t f 20 + 0.1 c b 2 300 ns fall time of scl and sda t sp 0 50 ns pulse width of suppressed spike c b 2 400 pf capacitive load for each bus line 1 a master device must provide a hold time of at least 300 ns for the sda signal (referred to the v ih minimum of the scl signal) to bridge the undefined region of the scl falling edge. 2 c b is the total capacitance of one bus line in pico farads (pf). timing diagram figure 2 i 2 c interface timing diagram s s p sr s = s t art condition sr = repe a ted s t art condition p = s t op condition scl sda t hd,dat t su,dat t hd,sta t su,sta t su,sto t high t r t f t f t sp t r t low t buf 1 1639-002 rev. a | page 8 of 64
data sheet adp5080 absolute maximum rat ings table 6. parameter rating vbatt to gnd ? 0.3 v to + 18 v vddio to gnd ?0.3 v to +4.0 v visw 1 to gnd ?0.3 v to +6.5 v visw 2 to gnd ?0.3 v to +4.0 v vreg 1 to gnd ? 0.3 v to + 6.5 v vreg 2 to gnd ? 0.3 v to + 4.0 v en to gnd ?0.3 v to +18 v en 34 to gnd ?0.3 v to + 6.5 v fault to gnd ? 0.3 v to + 4.0 v bstcp to pvincp ? 0.3 v to + 6.5 v bstcp to gnd ?0.3 v to +23 v c+ to pvincp ?0.3 v to (v vdr5 + 0.3 v) c? to pgnd 5 ?0.3 v to (v vdr5 + 0.3 v) pvinx to pgndx ? 0.3 v to + 18 v vdrx to pgndx ? 0.3 v to + 6.5 v bst16 , bst23 , bst45 to pvin x ? 0.3 v to + 6.5 v fb1 , fb 2, fb 3 to gnd ? 0.3 v to + 4.0 v fb4 , fb 5, fb 6 to gnd ? 0.3 v to + 6.5 v vout 6 to pgnd 6 ? 0.3 v to + 6.5 v sw 1a, sw1b to pgnd 1 ? 2.0 v to + 18 v sw 2 to pgnd 2 ? 2.0 v to + 18 v sw 3 to pgnd 3 ? 2.0 v to + 18 v sw 4 to pgnd 4 ?2.0 v to +18 v sw 5 to pgnd 5 ? 2.0 v to + 18 v sw 6 a to pgnd 6 ? 2.0 v to + 18 v sw 6 b to pgnd 6 ?0.5 v to ( v v out 6 + 2.0 v) or +6.5 v, whichever is lower pgndx to gnd ? 0.3 v to + 0.3 v vildo 7 to gnd ? 0.3 v to + 28 v voldo 7 to gnd ? 0.3 v to + 18 v freq to gnd ?0.3 v to ( v vreg 2 + 0.3 v) sync to gnd ? 0.3 v to + 4.0 v clko to gnd ?0.3 v to ( v vreg2 + 0.3 v) scl to gnd ? 0.3 v to + 4.0 v sda to gnd ? 0.3 v to + 4.0 v storage temperature range ? 65 c to + 150 c operating ambient temperature range ?2 5 c to + 85c operating junction te mperature range ? 25 c to + 125 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated i n the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for worst - case conditions; that is, a device soldered in a circuit board for surface - mount packages. n ote that actual ja depends on the application environment. table 7 . thermal resistance p cb type 1 ja 2 j b 2 unit 1s0p 60.6 7.3 c/w 2s2p 26.9 4.5 c/w 1 pcb t ype conform s to jedec jes d 51- 9 standard . 2 1.25 w power dissipation with zero airflow . esd caution rev. a | page 9 of 64
adp5080 data sheet pin configuration and function descrip tions figure 3 . pin configuration table 8 . pin f u nction descriptions pin no. mne monic description 1a vout6 out put voltage for channel 6 . 2a vout6 output voltage for channel 6 . 3 a visw1 input for an e xternal r egulator o utput . a 5.0 v to 5.5 v regulator connected to the visw1 pin can take over from ldo1 to supply the internal circuit of the adp5080 and the vreg1 load. if this pin is not used, connect it to gnd. 4a visw2 input for an e xternal r egulator o utput . a 3 .0 v to 3 . 3 v regulator connected to the visw 2 pin can take ov er from ldo 2 to supply the internal circuit of the adp5080 and the vreg 2 load. if this pin is not used, connect it to gnd. 5a pvincp input power supply for the charge pump . 6a c+ flying capacit or terminal for the charge pump . 7a pgnd5 power ground for channel 5 . 8a sw5 switching node for channel 5 . 9a pvin5 input power supply for channel 5 . 1b sw6b secondary side boost switching node for channel 6. 2b sw6b secondary side boost switching nod e for channel 6 . 3 b vreg1 output voltage for ldo1 . 4b vreg2 output voltage for ldo2 . 5b voldo7 output voltage for channel 7. leave this pin open if not used. 6b c? flying capacitor terminal for the charge pump . 7b pgnd5 power ground for channel 5 . 8b sw5 switching node for channel 5 . 9b pvin5 input power supply for channel 5 . 1c pgnd6 power ground for channel 6 . 2c pgnd6 power ground for channel 6 . 3c vbat t p ower supply input for the internal circuits. connect this pin to the battery. 4c en34 independent enable i nput for c hannel 3 and c hannel 4. if this pin is not used, connect it to gnd. 5 c vildo7 input power supply for channel 7. if this pin is not used, c onnect it to vbat t . 6c bstcp output voltage for charge pump . 7c vdr5 low - side fet driver power supply for channel 5 . connect this pin to vreg1 . 8c bst45 high - s ide fet driver power supply for channel 4 and channel 5 . vout6 vout6 visw1 visw2 pvincp c+ sw5 vreg2 voldo7 c? en34 vildo7 bstcp sw5 pvin5 pvin5 pvin4 bst45 sw6b sw6b vreg1 pgnd6 pgnd6 vbatt sw6a sw6a vdr6 sw4 vdr34 pgnd4 pgnd3 pgnd3 sw3 pvin3 fb6 gnd sync pvin6 pvin6 bst16 scl gnd pvin1 pvin1 fb1 sw2 sw1b vdr12 pgnd1 fault pgnd2 en vddio freq sw2 pvin2 pvin3 pgnd1 sw1a fb4 sda gnd sw3 fb2 pgnd5 pgnd5 vdr5 clko fb3 gnd bst23 fb5 t op view (bal l side down) not to scale 1 1639-003 1 a b c d e f g 2 3 4 bal l a1 corner 5 6 7 8 h 9 rev. a | page 10 of 64
data sheet adp5080 pin no. mne monic description 9c pvin4 input power supply for chan nel 4 . 1d sw6a primary side switching node for channel 6 . 2d sw6a primary side switching node for channel 6 . 3d vdr6 low - side fet driver power supply for channel 6 . connect this pin to vreg1 . 4 d fb6 feedback node for channel 6 . 5d gnd ground. all gnd pins must be connected. 6d sync external clock input ( cmos i nput p ort ) . if this pin is not used, connect it to gnd. 7d fb5 feedback node for channel 5 . 8d fb4 feedback node for channel 4 . 9d sw4 switching node for channel 4 . 1 e pvin6 input power suppl y for channel 6 . 2e pvin6 input power supply for channel 6 . 3e bst16 high - s ide fet driver power supply for channel 1 and channel 6 . 4e sda data input/output for i 2 c interface. open - drain i/o port . 5e scl clock input for i 2 c interface . for start - up requ irements, see the i 2 c interface section. 6e gnd ground. all gnd pins must be connected . 7e clko clock output ( cmos o utput p ort ) . clko replicates the c hannel 1 switching clock. this o utput is not available when the sync pin is dr iven by an external clock . if this pin is not used, leave it open. 8e vdr34 low - side fet driver power supply for channel 3 and channel 4 . connect this pin to vreg1 . 9e pgnd4 power ground for channel 4 . 1f pvin1 input power supply for channel 1 . 2 f pvin 1 input power supply for channel 1 . 3f fb 1 feedback node for channel 1 . 4f en enable control input . 5f vddio supply voltage for i 2 c i nterface. typically, this pin is connected externally to vreg2 or to the host i/o voltage . 6f freq frequency pin for th e internal oscillator . to select the i nternal clock source oscillator , connect an e xternal 100 k resist o r from the freq pin to gnd. 7f fb3 feedback node for channel 3 . 8f pgnd3 power ground for channel 3 . 9f pgnd3 power ground for channel 3 . 1g sw1a s witching node for channel 1 . 2g sw1b switching node for channel 1 . 3 g vdr12 low - side fet driver power supply for channel 1 and channel 2 . connect this pin to vreg1 . 4g fb2 feedback node for channel 2 . 5g gnd ground. all gnd pins must be connected . 6g fault f ault status output pin. this o pen - drain output port goes low when a fault occurs. leave open if not used. 7g gnd ground. all gnd pins must be connected . 8g sw3 switching node for channel 3 . 9g sw3 switching node for channel 3 . 1h pgnd1 power ground for channel 1 . 2h pgnd1 power ground for channel 1 . 3h pgnd2 power ground for channel 2 . 4h sw2 switching node for channel 2 . 5h sw2 switching node for channel 2 . 6h pvin2 input power supply for channel 2 . 7h bst23 high - s ide fet driver power supply for channel 2 and channel 3 . 8h pvin3 input power supply for channel 3 . 9h pvin3 input power supply for channel 3 . rev. a | page 11 of 64
adp5080 data sheet typical performance characteristics figure 4 . channel 1 efficiency , v out = 1.1 v f igure 5 . channel 2 efficiency, v out = 1.2 v figure 6 . channel 3 efficiency, v out = 1.8 v figure 7 . channel 4 efficiency, v out = 3.3 v figure 8 . channel 5 efficiency, v out = 3.3 v figure 9 . channel 6 efficiency, v out = 5 v 0 10 20 30 40 50 efficienc y (%) 60 70 80 90 100 10 100 output current (ma) 1000 v in = 4. 5 v v in = 7. 2 v v in = 1 2 .6 v au t o psm fpwm 1 1639-004 0 10 20 30 40 50 efficienc y (%) 60 70 80 90 100 10 100 output current (ma) 1000 v in = 4. 5 v v in = 7. 2 v v in = 1 2 .6 v 1 1639-005 fpwm au t o psm 0 10 20 30 40 50 efficienc y (%) 60 70 80 90 100 10 100 output current (ma) 1000 v in = 4. 5 v v in = 7. 2 v v in = 1 2 .6 v fpwm 1 1639-006 au t o psm 0 10 20 30 40 50 efficienc y (%) 60 70 80 90 100 10 100 output current (ma) 1000 v in = 4. 5 v v in = 7. 2 v v in = 1 2 .6 v au t o psm fpwm 1 1639-007 0 20 10 40 efficienc y (%) 60 80 30 50 70 90 100 10 100 output current (ma) 1000 1 1639-008 fpwm au t o psm v in = 4. 5 v v in = 7. 2 v v in = 1 2 .6 v 0 10 20 30 40 50 efficienc y (%) 60 70 80 90 100 10 output current (ma) 100 1000 1 1639-009 au t o psm fpwm v in = 4. 5 v v in = 7. 2 v v in = 1 2 .6 v rev. a | page 12 of 64
data sheet adp5080 figure 10 . channel 1 load regulation figure 11 . channel 2 load regulation figure 12 . channel 3 load regulation figure 13 . channel 4 load regulation figure 14 . channel 5 load regulation figure 15 . channel 6 load regulation 1.090 1.095 1.100 1.105 1. 1 10 0.1 1 10 100 1000 v in = 4. 5 v v in = 7. 2 v v in = 1 2 .6v output vo lt age (v) 1 1639-010 output current (ma) 1.190 1.192 1.194 1.196 1.198 1.200 1.202 1.204 1.206 1.208 1.210 0.1 1 10 100 output vo lt age (v) 1 1639-0 1 1 output current (ma) 1000 v in = 4. 5 v v in = 7. 2 v v in = 1 2 .6v 1.790 1.795 1.800 1.805 1.810 0.1 1 10 100 1000 v in = 4. 5 v v in = 7. 2 v v in = 1 2 .6v output vo lt age (v) 1 1639-012 output current (ma) 3.285 3.290 3.295 3.300 3.305 3.310 3.315 0.1 1 10 100 1000 v in = 4. 5 v v in = 7. 2 v v in = 1 2 .6v output vo lt age (v) 1 1639-013 output current (ma) 3.280 3.285 3.290 3.295 3.300 3.305 3.310 3.315 3.320 0.1 1 10 100 1000 v in = 4. 5 v v in = 7. 2 v v in = 1 2 .6v output vo lt age (v) 1 1639-014 output current (ma) 4.980 4.985 4.990 4.995 5.000 5.005 5.010 5.015 5.020 0.1 1 10 100 1000 output vo lt age (v) 1 1639-015 output current (ma) v in = 4. 5 v v in = 7. 2 v v in = 1 2 .6v rev. a | page 13 of 64
adp5080 data sheet figur e 16 . channel 7 load regulation , vildo7 = 16 v figure 17 . vreg 1 load regulation figure 18 . vreg 2 load regulation figure 19 . channel 1 load trans ient , v out = 1.1 v , fpwm mode figure 20 . channel 1 load transient, v out = 1.1 v , auto psm mode figure 21 . channel 2 load transient , v out = 1.2 v , fpwm mode 1 1.95 1 1.96 1 1.97 1 1.98 1 1.99 12.00 12.01 12.02 12.03 12.04 12.05 0.1 1 10 output vo lt age (v) output current (ma) 1 1639-016 4.900 4.925 4.950 4.975 5.000 5.025 5.050 5.075 5.100 0.1 1 10 100 vreg1 output vo lt age (v) output current (ma) 1 1639-017 3.200 3.225 3.250 3.275 3.300 3.325 3.350 3.375 3.400 0.1 1 10 100 1 1639- 1 18 vreg2 output vo lt age (v) output current (ma) 2 4 ch2 20.0mv b w 20.0m 200s/div 20.0ms/s ch4 500m a 50? b w 250m 1 1639-018 2 4 ch2 20.0mv b w 20.0m ch4 300m a 50? b w 20.0m 1 1639-127 200s/div 10.0ms/s 2 4 ch2 20.0mv b w 20.0m ch4 300m a 50? b w 250m 1 1639-019 200s/div 20.0ms/s rev. a | page 14 of 64
data sheet adp5080 figure 22 . ch annel 2 load transient, v out = 1. 2 v , auto psm mode figure 23 . channel 3 load transient , v out = 1.8 v , fpwm mode figure 24 . channel 3 load transient, v out = 1. 8 v , auto psm mode figure 25 . channel 4 load transient , v out = 3.3 v , fpwm mode figure 26 . channel 4 load transient, v out = 3.3 v , auto psm mode figure 27 . channel 5 load transient , v out = 3.3 v , fpwm mode 2 4 ch2 20.0mv b w 20.0m ch4 200m a 50? b w 20.0m 1 1639-128 200s/div 20.0ms/s 2 4 ch2 40.0mv b w 20.0m ch4 400m a 50? b w 250m 1 1639-020 200s/div 20.0ms/s 2 4 ch2 50.0mv b w 20.0m ch4 200m a 50? b w 20.0m 1 1639-129 200s/div 20.0ms/s 2 4 ch2 20mv b w 20.0m ch4 200m a 50? b w 250m 1 1639-021 200s/div 5.0ms/s 2 4 ch2 50.0mv b w 20.0m ch4 100m a 50? b w 20.0m 1 1639-130 200s/div 20.0ms/s 2 4 ch2 50.0mv b w 20.0m ch4 500m a 50? b w 250m 1 1639-022 200s/div 20.0ms/s rev. a | page 15 of 64
adp5080 data sheet figure 28 . channel 5 load transient, v out = 3.3 v , auto psm mode figure 29 . channel 6 load transient , v out = 5 v , fpwm mode figure 30 . channel 6 load transient, v out = 5 v , auto psm mode figure 31 . vreg1 load transient , vreg1 = 5 v figure 32 . vreg2 load transient , vreg 2 = 3.3 v 2 4 ch2 50.0mv b w 20.0m ch4 300m a 50? b w 20.0m 1 1639-131 200s/div 20.0ms/s 2 4 ch2 70.0mv b w 20.0m ch4 400m a 50? b w 1.0g 1 1639-023 200s/div 20.0ms/s 2 4 ch2 100mv b w 20.0m ch4 300m a 50? b w 20.0m 1 1639-132 200s/div 20.0ms/s 2 4 ch2 100mv b w 20.0m ch4 100m a 50? b w 250m 1 1639-125 200s/div 20.0ms/s 2 4 ch2 20mv b w 20.0m ch4 100m a 50? b w 250m 1 1639-126 200s/div 20.0ms/s rev. a | page 16 of 64
data sheet adp5080 figure 33 . startup figure 34 . sh utdown r3 r4 2 3 4 r1 1 r2 ch1 1.0v 1m? ch7 ch5 ch6 ch4 ch2 ch3 ch1 en ch2 2.0v 1m? ch3 5.0v 1m? ch4 5.0v 1m? r1 1.0v 1.0ms r2 1.0v r3 5.0v r4 2.0v 1 1639-026 r1 r4 2 3 4 1 r2 r3 ch1 5.0v 1m? ch7 ch5 ch6 ch4 ch2 ch3 ch1 en ch2 3.0v 1m? ch3 1.0v 1m? ch4 5.0v 1m? r1 5.0v 2.0ms r2 1.0v r3 700mv r4 3.0v 1 1639-027 rev. a | page 17 of 64
adp5080 data sheet application circuit figure 35 . typical application circuit i 2 c interface key controller/ sub-cpu vreg2 vreg2 power switch en vddio scl sda vbatt fb4 fb2 pgnd4 bst16 sw1a sw1b pvin1 fb1 pgnd1 sw3 sw3 fb3 pgnd3 pgnd3 sw5 sw5 fb5 pgnd5 pgnd5 vdr12 pgnd1 sw6b sw6b pgnd6 pvin6 pvin6 sw6a vbatt vout6 vdr6 pgnd6 vout6 sw6a vbatt vbatt vbatt vbatt vbatt vddio vbatt vreg1 vreg1 gnd pvin5 pvin4 sw4 pvin5 vreg1 to vdrx 5.0v vreg2 c+ c? pvincp vildo7 voldo7 freq sync bstcp fault c+ bst45 vdr5 (v dr 1 2) (b st4 5) vbatt vreg1 bstcp bstcp pvin1 pgnd1 bstcp pvin3 pvin3 (b st2 3) (b st16) vdr34 vreg1 (v dr 3 4) clko gnd bstcp bstx gnd en34 gnd visw1 visw2 3.3v pgnd6 pgnd6 pgnd3 pgnd5 pgnd4 pgnd2 fb6 pvincp output enable logic v out 1 v out 3 v out 2 v out 5 v out 4 v out 6 100k? optional uvlo pgnd2 sw2 sw2 pvin2 fault bst23 c hannel 7 h v ld o o sci ll at or power fault detection channel 1 buck regulator channel 2 buck regulator channel 3 buck regulator channel 4 buck regulator channel 5 buck regulator dac soft start comp discharge switch dac dac soft start comp discharge switch dac soft start comp discharge switch gate scaling channel 6 buck/ buck boost regulator c ha rg e p um p soft start comp discharge switch dac soft start comp discharge switch dac soft start comp discharge switch uvlo ldo1 (keep-alive) ldo2 (keep-alive) vddio vddio por 4.7f 4.7f 1f 10f 12v power sequence 1 1639-028 rev. a | page 18 of 64
data sheet adp5080 theory of operation the adp5080 is a fully integrated, high efficiency power solu - tion for mult i cell lithium ion battery applications. the device can connect directly to the battery, which eliminates the need for preregulators and increases the battery life of the system. the adp5080 integ rates two keep - alive ldo regulator s , five synchronous buck regulators , one configurable buck boost regu - lator, and one high voltage ldo regulator . a n integrated charge pump provide s the switch driver power supply. along with the integrat ed power fets and d rivers, integrated compensation , s oft start, and fb dividers contribute to minimize the number of external components and the pcb layout space , provid ing significant advantage s for portable applications . factory programming sets the default values for the output voltage s , fault behavior, switching frequency , start - up time, and other functions. these values can also be programmed via the i 2 c interface. the adp5080 features a built - in sequencer that provides automatic startup and shutdown timing based on these settings. uvlo and por the undervoltage lockout (uvlo) and power - on reset (por) functions prevent abnormal behavior and force a smooth shut - down when input voltages fall below the minimum requi red levels. the adp5080 incorporates uvlo on vbatt, pvin1, and vdr12 ; it incorporates por on vreg2. t h e thresholds are low enough to ensure normal operation down to 4 v at vbatt with ample hyster esis to avoid chattering. undervoltage lockout (uvlo) if the pvin 1 voltage of channel 1 falls below the uvlo threshold (v uvlo ( f) ), all channels , as well as the charge pump , are turn ed off. however, ldo1 and ldo2 remain operational . as the input voltage ri ses , the regulator channels do not restart automatically. en must be toggled after a uvlo event to restart channels in sequencer mode or manual mode. for more informa - tion about enabling channels using sequencer mode and manual mode, see the e nabling and d isabling the output c hannels section. the vdrx pins provide the gate drive voltage to the internal power fets. if the vdr12 voltage falls below 2.9 v (typical), all channels except ldo1 and ldo2 shut do wn to prevent malfunction of the power f ets. a s with a pvin uvlo event, en must be toggled to restart channel operation. power - on reset (por) if the vbatt voltage falls below its uvlo threshold (v uvlo ( batt) ), all channels , including ldo1 and ldo2 , are shu t down. this event forces a power - on reset . vreg2 is the voltage supply for the internal digital circuit blocks. if the vreg2 voltage falls below the power - on reset threshold (v uvlo ( por) ) of 2.4 v typical, the adp5080 shut s down , and all registers are reset to their default values. discharge switch the adp5080 integrates discharge switches for channel 1 to channel 7 . these switches help to discharge the output capacitors quickly when a channel is turned off. the discharge switches are turned on when the en signal goes low or when a channel is manually turned off via i 2 c control , provided that the discharge function was enabled by setting the dscg x _on bit ( x is 1 to 7 ) in register 1. the d efault value s for the discharge switches are factory fuse programmed. keep - alive ldo r egulators the k eep - a live ldo linear regulators ( ldo1 and ldo2 ) are kept alive as long as a valid supply voltage is app lied to the vbatt pin. the ldo regulator s are used to power the internal control block of the adp5080 so that the device is ready for the enable ( en ) signal. the outputs of ldo 1 and ldo2 are also available via the vreg1 and vreg2 pins for external circuits that are also kept alive during system stand by. when vbatt initially rises above the uvlo threshold, ldo1 begins operati on , followed by ldo2. when all uvlo threshold s are cleared, the adp5080 is in standby mode and ready to be enable d . if an external voltage is used to drive vddio, vddio can be on before vbatt ; otherwise , ldo2 provides power to vddio via the vreg 2 output. rev. a | page 19 of 64
adp5080 data sheet ldo1 ldo1 reg ulates the supply voltage applied to the vbatt pin to either 5.0 v or 5.5 v and is capable of providing up to 4 00 ma. ldo1 internally supplies ldo2, as well as external circuits , includ - ing the vdrx pins supplied through the vreg 1 pin. the ldo1 output is e nabled when the vbatt pin voltage rises above the uvlo threshold and is disabled when the vbatt pin voltage falls below the uvlo threshold . visw1 input a 5.0 v to 5.5 v r egulator connected to the visw1 pin c an take over from ldo1 to supply the internal circuit of the adp5080 and the vreg1 lo ad. to en able this f eature, s e t the sel_inp_ldo1 bit (bit 0 in register 3 3) hig h after the visw1 p in v oltag e settles above 4.7 v. if t he visw1 pin voltage fall s below 4.5 v , ldo1 resumes control automatically . however, if the visw1 source is disabled , it is recommended that the sel_inp_ldo1 bit be reset to 0 before turning off the visw1 pin source. th e use of an external regulator connected to the visw1 pin is intended to achieve better system power efficiency by allowing a switching power supply to take over the ldo1 linear regulator when the system is powered up to operation. if the visw1 input is not used, tie it to gnd. the visw1 input is not active until en is high. current limit for ldo1 ldo1 is rated to a maximum load current of 4 00 ma . above this level, the current - limit feature limit s the current to protect the device. the visw1 i nput has an independent current - limit circuit with a typical threshold of 5 00 ma. if this over current threshold is exceeded , the visw1 input is immediately disconnect ed and ldo1 take s over to supply the vreg1 current. after the visw1 input is turned off due to a current - limit event, it can be reset only by toggling the en pin. di scharge switch for ldo1 a discharge switch at the vreg1 pin turns on during low vbatt pin voltage (3.5 v 0.1 v h ysteresis ), removing the charge of the external capacitor via a 1 k? resistor . f igure 36 . vreg1, ldo1, and visw1 current detection visw1 vreg1 agnd vbatt vref ldo1 overcurrent protection discharge switch to internal circuits 5.0v or 5.5v 5.0v to 5.5v voltage detection overcurrent protection 1 1639-029 rev. a | page 20 of 64
data sheet adp5080 ldo2 ldo2 regulates the internally routed vreg 2 pin voltage to 3 v , 3.15 v , 3.2 v , or 3.3 v and is capable of providing up to 300 ma. ldo2 internally supplies the control block of the adp5080 , as well as external circuits supplied through the vreg2 pin. the ldo 2 output is enabled when the vbatt pin voltage rises above the uvlo threshold and is disabled when the vbatt pin voltage falls below the uvlo threshold . visw2 input a 3 .0 v to 3 .3 v regu lator connected to the visw 2 pin can take over from ldo 2 to supply the internal circuit of the adp5080 and the vreg 2 load. to enable this feature , set the sel_inp_ldo 2 bit (bit 4 in register 33) high after the visw 2 pin voltage settle s above 2 .7 v. if the visw 2 pin voltage falls below 2 .5 5 v , ldo 2 resumes control automatically . however, if the visw 2 source is disabled , it is recommended that the sel_inp_ldo 2 bit be reset to 0 before turning off th e visw 2 pin source. th e use of an external regulator connected to the visw2 pin is intended to achieve better system power efficiency by allowing a switching power supply to take over the ldo 2 linear regulator when the system is powered up to operation. i f the visw 2 input is not used, tie it to gnd. the visw 2 input is not active until en is high. because th e visw2 input supplies vreg2 with no regulation, the maximum voltage that can be applied to visw2 is 3.3 v. the visw2 input has a relatively high resist ance compared to the ldo2 path. as a result, visw2 regulation may not be sufficient when used to supply heavier loads. current limit for ldo2 ldo 2 is rated to a maximum load current of 300 ma . above this level, the current - limit feature limit s the current to prote ct the device. the visw 2 input has an independe nt current - limit circuit with a typical threshold of 3 00 ma. if this overcurrent threshold is exceeded , the visw 2 input is immediately disconnect ed and ldo 2 take s over to supply the vreg 2 current. afte r the visw 2 input is turned off due to a current - limit event, it can be reset only by toggling the en pin. discharge switch for ldo2 a discharge switch at the vreg 2 pin turns on during low vbatt pin voltage (3.5 v 0.1 v h ysteresis ), removing the residual charge of the external capacitor via a 12 ? resist or . figure 37 . vreg2, ldo2, and visw2 current detection visw2 vreg2 agnd from vreg1 output 5.0v to 5.5v ldo2 vref overcurrent protection discharge switch to internal circuits 3.0v to 3.3v 3.0v to 3.3v voltage detection overcurrent protection 1 1639-030 rev. a | page 21 of 64
adp5080 data sheet dc -to - dc c onverter channels the adp5080 integrates five buck regulators and a configurable buck only/buck boos t regulator. these regulators c an be con figured for various functions including a uto psm, a uto dcm, dvs , and g ate s caling. each function is included only in the channels where it is most effective ( see tabl e 9 ). ch annel 1 , channel 2 , and channel 3: buck regulator s with flex - mode architecture channel 1 , channel 2 , and channel 3 feature flex - mode ? current mode control , which eliminates minimum on time requirements and allows duty cycles as low as 0%. flex - mode uses a unique adaptive control architecture that maintains stable operation over a wide range of application conditions. with flex - mode control, very high step - down ratios can be achieved while maintaining high efficiency and excellent transient performance. sele cting the output voltage , channel 1 to channel 3 the o utput voltage of c hannel 1, channel 2, or channel 3 is selected from one of the preset values available in the vidx bits, where x is 1, 2, or 3 (see table 39 an d table 41). the default o utput voltage value is factory fuse programmed. c hannel 3 has a n a djustable mode option that can be selected using the vid3 bits . when the adjustable output voltage mode is selected, the o utput voltage is set by an external feedback resistor divider. select resistor values such that the desired output voltage is divided down to 0.8 v and the paralleled resistance seen from the dividing node does not exceed 25 k? (see the setting the output voltage ( a djustable mode c hannels) section). channel 1 can also be used in adjustable output mode by setting the vid1 bits to 0.8 v and us ing external feedback resistor s with values less than 1 k?. when using the adjustable mode for channel 1 or channel 3 , be aware of t he minimum off time restriction , which may limit the range of available output voltage s. channel 1, channel 2 , and channel 3 are designed for very low duty cycle operat ion. however, at very high duty cycle, these chan - nels have a limited range due to the minimum off time restriction ( see table 3 ). the minimum input voltage capability for a given output voltage can be determined u sing the following equation: v in_min = v out /(1 ? t off_min f sw ) if the input voltage falls below this level, the output voltage droop s below its nominal value . current - limit protection , channel 1 to channel 3 channel 1, channel 2 , and channel 3 use valley mode current limit (see figure 38). in valley mode current - limit protection , inductor current is sensed during the low - side on cyc le, imme - diately before the high - side fet turns on. if the inductor current is above the current - limit threshold at th is point , the next switching pulse is skipped. figure 38 . valley mode current limit switching does not resume until the current falls below the limit threshold. this behavior creates an inherent frequency foldback feature, which makes va lley mode current - limit protection very robust against runaway inductor current. because this type of current limit senses current before switching, it is also relati vely immune to switching noise. table 3 provide s the valley current threshold specifications . the actual load current - limit threshold var ies with inductor value, frequency, and input and output voltage. when the current - limit threshold is exceeded, load current is not allowed to increase further. theref ore, as the load impedance is reduced, the current limit force s the output voltage to fall . the falling output voltage in turn toggle s the pwrg x , uv x, and faul t error flags . in the extreme event of an output voltage short circuit, the uvp function protect s the device against excessive current during the on cycle (see the undervoltage protection (uvp) section) . table 9. dc -to - dc converter specifications and functions channel regulator type v in range (v) v out range (v) adj ustable mode (v) i out (a) auto psm auto dcm dvs gate scaling 1 buck 4 to 15 0.8 to 1.2 1 0.8 to 1.2 3 yes n/a yes yes 2 buck 4 to 15 1.0 to 3.3 n/a 1.1 5 yes n/a yes n/a 3 buck 4 to 15 1.2 to 1.8 0.8 to 3.6 1.5 yes n/a n/ a n/a 4 buck 4 to 15 1.8 to 3.55 1.0 to 5.0 0.8 yes n/a n/a n/a 5 buck 4 to 15 3.0 to 5.0 n/a 2 yes yes n/a n/a 6 buck or buck boost 4 to 15 3.5 to 5.5 1.0 to 5.0 2 (b uck) 1.5 ( b uck b oost) yes yes n/a n/a 1 chann el 1 has two available voltage ranges. valley current- limit threshold sw node inductor current current sensing point skipped cycle 1 1639-031 rev. a | page 22 of 64
data sheet adp5080 discharge switch , channel 1 to channel 3 ea ch channel incorporates a discharge switch . for channel 1 and channel 2, the discharge switch is located at the fb1 and fb 2 pin s , respectively; for channel 3, the discharge switch is located at the sw3 pin . the discharge switch can be turned on when the co rresponding channel output is turned off, removing the residual charge of the external capacitor via a 125 ? resist or . the discharge switch can be e nabled by setting the appropriate dscg x_on bit in register 1. gate scaling (channel 1 o nly) c hannel 1 features a gate scaling function , which improves efficiency in light load conditions. when enabled by setting th e gate_scal1 bit in register 32 , gate scaling halves the size of the c hannel 1 switching fets, redu cing the gate charge - up current which is a non - negligible loss element in light load conditions while allowing increased r dson , whose effect is less signific ant in these conditions. when g ate s caling is enabled, only sw1a is used for the channel 1 switch node because it is assumed that the load current is light. dynamic voltage scaling (dvs) function channel 1 and channel 2 incorporate a d ynamic v oltage s calin g (dvs) function . dvs provides a stair - step trans ition in output volt - age when the preset value for the output voltage is re programmed on the fly ( see figure 39). figure 39 . dvs oper ation the output voltage for channel 1 is programmed using the vid1 bits in register 12; the output voltage for channel 2 is programmed using the vid2 bits in register 13. when the dvs function is enabled , the voltage transition takes place according to th e steps set by the vid1 or vid2 bits (see table 39 and table 41 ). the transition time from one step to the next is specified by the interval programmed in register 17 using the dvs x _ i n t va l bits ( where x is 1 or 2) . th e dvs function is enabled by setting the en_dvs x bit in register 17. for channel 2, dvs operation is limited to an output voltage range of 1.0 v to 1.25 v. when channel 1 or channel 2 is configured for dvs opera tion, toggling en low does not immediately reset the vid code to i ts i nitial state. instead c hannel 1 or channel 2 return s to its config - ured output vol tage according to the steps set by the vid1 or vid2 bits (see table 39 and table 41 , respectively) . figure 40 . buck regulato r block diagram : channel 1 , channel 2 , and channel 3 output voltage dvsx_intval vid (new) vid (prev) vid (prev ? 1) 1 1639-032 shoot-through protection pvinx swx pgndx fbx pgnd pgndx 4v to 15v power-good comparator soft start fb1 fb2 sw3 error amp pwm comparator pgndx current sense amp bstx vdrx vreg1 pgndx ovp uvp ocp sequencer rs latch r s psm logic zero cross comparator discharge switch bstcp current limit ocp vref on period slope generation clock output voltage output voltage fb3 0.8v external voltage divider (ch3 adj mode only) 1 1639-033 adp5080 rev. a | page 23 of 64
adp5080 data sheet channel 4 and channel 5: current mode buck regulato rs channel 4 and channel 5 are internally compensa ted current mode control buck regulators (see figure 41) . combined with the integrated charge pump, these channels are designed to operate at high duty cycles up to 100%. selecting the output voltage , channel 4 and channel 5 the o utput voltage of c hannel 4 or channel 5 is selected from one of the preset values available in the vid x bits, where x is 4 or 5 (see table 43 ) . the default o utput voltage value is factory fuse progr ammed. c hannel 4 has a n a djustable mode option that can be selected using the vid 4 bits . when the adjustable output voltage mode is selected, the output voltage is set by an external feedback resistor divider. select resistor values such that the desired o utput voltage is divided down to 0.8 v and the paralleled resistance seen from the dividing node does not exceed 25 k? (see the setting the output voltage ( a djustable mode c hannels) section). when using the adjustable mode for channel 4 , be aware of the minimum o n time restriction , which may limit the range of available output voltage s. channel 4 and channel 5 are designed for very high duty cycle operation. however, at very low duty cycle, these channels have a limited range due to the minimum o n time restriction ( 75 ns typical) inherent in current mode control . the m ax imum inp ut voltage capability for a given output voltage can be determined using the following equation: v in_max = v out /( t on_min f sw ) if the input voltage rises above this level, the output voltage continue s to be regulated ; however , switching pulses are skipped , which may increase output voltage ripple. figure 41 . buck regulator block diagram : channel 4 and channel 5 shoot-through protection pvinx swx pgndx fbx pgnd pgndx 4v to 15v power-good comparator soft start fb5 sw4 error amp vref pwm comparator pgndx current sense amp bstx vdrx vreg1 pgndx ovp uvp ocp sequencer rs latch r s psm logic zero cross comparator discharge switch bstcp current limit ocp slope compensation clock output voltage output voltage fb4 0.8v external voltage divider (ch4 adj mode only) 1 1639-034 adp5080 rev. a | page 24 of 64
data sheet adp5080 rev. a | page 25 of 64 current-limit protection, channel 4 and channel 5 channel 4 and channel 5 have integrated cycle-by-cycle current- limit protection. in this type of current-limit protection, inductor current is sensed throughout the high-side on cycle. if the inductor current rises above the current-limit threshold during this time, the switching pulse is immediately terminated until the next cycle. this behavior causes the duty cycle to decrease, which in turn causes the output voltage to fall. the falling output voltage then toggles the pwrgx, uvx, and fault error flags. because there is substantial parasitic noise at the rising edge of the high-side switch, some blanking time is required to prevent false current-limit triggering. this required blanking time determines the minimum on time of the channel. unlike valley mode current-limit protection, peak mode current- limit protection has no inherent frequency foldback. in extreme conditions such as a short circuit or inductor saturation, peak mode current limit is susceptible to runaway inductor current. to prevent this, the adp5080 provides frequency foldback on channel 4, channel 5, and channel 6. when the output voltage falls below approximately 80% of its nominal value, the switch- ing frequency is halved. the frequency is halved again if the output voltage falls below approximately 40% of its nominal value. the frequency foldback feature allows more time for inductor current to decay, eliminating the possibility of current runaway. table 3 provides the peak current-limit threshold specifications. the actual load current-limit threshold varies with inductor value, frequency, and input and output voltage. discharge switch, channel 4 and channel 5 each channel incorporates a discharge switch. for channel 4, the discharge switch is located at the sw4 pin; for channel 5, the discharge switch is located at the fb5 pin. the discharge switch can be turned on when the corresponding channel output is turned off, removing the residual charge of the external capacitor via a 125 resistor. the discharge switch can be enabled by setting the appropriate dscgx_on bit in register 1. channel 6: buck or buck boost regulator channel 6 is a current mode control, four-switch buck boost regulator that can be configured as a buck only regulator. in a system in which the input voltage never falls below the channel 6 output, using the buck only configuration reduces the losses caused by the switching fets of the boost side. the buck only configuration yields better power efficiency, as well as lower output ripple and noise. buck only configuration for the buck only configuration, set the buck6_only bit (bit 4 in register 30) to 1. the default value of this bit is factory fuse programmed. when channel 6 is configured for buck only mode, connect the inductor between the sw6a and vout6 pins, leaving the sw6b pin open (see figure 42). this configuration bypasses the boost side switching fet. buck boost configuration for the buck boost configuration, set the buck6_only bit (bit 4 in register 30) to 0. the default value of this bit is factory fuse programmed. for the buck boost configuration, connect the inductor between the sw6a and sw6b pins (see figure 42). make sure that no capacitor is connected to the sw6b pin. in buck boost operation, channel 6 automatically switches between the buck and boost modes as the input voltage varies. ? in buck mode, the primary fets (sw6a) switch with the sw6b high-side fet operating at 100% duty cycle. ? in boost mode, all four fets are typically switching, although the primary high-side fet is capable of a 100% duty cycle. when the input voltage is close to the output voltage, channel 6 operates in buck boost mode with all four power fets switching. this four-switch mode of operation ensures a smooth transition and excellent regulation, regardless of input voltage conditions. the boost6_vth bits (bits[1:0] in register 30) set the input voltage threshold for the boost fets to start switching. a lower threshold provides higher efficiency because the region where all four switches are in operation is smaller. the lowest setting for these bits (11) sets an input voltage threshold that is still high enough to prevent dropout in most cases. however, under heavy load current at the lowest threshold setting, the buck side may reach a 100% duty cycle and some output droop may occur. the second lowest setting for these bits (00) is recommended for heavy load applications. the default value of these bits is factory fuse programmed. selecting the output voltage, channel 6 the output voltage of channel 6 is selected from one of the preset values available in the vid6 bits (see table 45). the default output voltage value is factory fuse programmed. channel 6 has an adjustable mode option that can be selected using the vid6 bits. when the adjustable output voltage mode is selected, the output voltage is set by an external feedback resistor divider. select resistor values such that the desired output voltage is divided down to 0.8 v while the paralleled resistance seen from the dividing node does not exceed 25 k (see the setting the output voltage (adjustable mode channels) section). because channel 6 can operate in boost mode, there is no practical output voltage limitation other than the maximum rating. when using the adjustable output voltage in buck only mode, be aware of the minimum on time restriction, which may limit the range of available output voltages. the minimum on time limitation is essentially the same as for channel 4 and channel 5 (see the selecting the output voltage, channel 4 and channel 5 section).
adp5080 data sheet current - limit protection , channel 6 like channel 4 and channel 5, channel 6 has integrated cycle - by - cycle current - limit protection . in this type of current - li mit protection , inductor current is sensed throughout the high - side on cycle. the channel 6 current limit is sensed on the primary high - side fet (sw6a). for more information, see the current - limit protection , channel 4 and channel 5 section. discharge switch , channel 6 each channel incorporates a discharge switch . for channel 6, the discharge switch is located at the vout6 pin. the discharge switch can be turned on when the channel 6 output is turned off, removing the residual char ge of the external capacitor via a 1 10 ? resist or . the discharge switch can be e nabled by setting the dscg 6_on bit in register 1 . figure 42 . channel 6 buck or buck boost regulator block diagram sw6a vdr6 vreg1 sw6b adp5080 adp5080 pgnd6 sw6a sw6b buck only configuration buck boost configuration vout6 pgnd6 fb6 open pgnd6 pgnd6 4v to 15v power-good comparator soft start error amp pwm comparator current sense and limit ocp ovp pgnd6 uvp ocp sequencer rs latch s q r psm logic zero cross comparator vref discharge switch slope compensation clock clock vout6 fb6 0.8v external voltage divider (adj mode only) vout6 vout6 pgnd6 pgnd6 pgnd6 3.5v to 5.5v fb6 vout6 fb6 0.8v external voltage divider (adj mode only) 3.5v to 5.5v control logic control logic bstcp bst16 pvin6 1 1639-035 rev. a | page 26 of 64
data sheet adp5080 light load and other modes o f operation for the dc - to- dc converter channel s each dc - to - dc converter channel in the adp5080 has two or three options to handle light load conditions , where as asyn - chronous dc - to - dc converters simply transition to discontinuous conduction mode (dcm) . although light load modes provide higher efficiency and longer battery life, they are also associated with increased ripple and noise. this trade - off requires the user to select the option that best suits the application, usually on a channel by channel basis (see table 9 ) . the modes of operation are illustrated in figure 43 , which shows the inductor current and the switch node in au to psm, auto dcm , and fpwm modes. slew rate adjust ment each channel has a slew rate adjust ment option , which is set using the adj_srx bit (where x is 1 to 6) in the opt_sr _adj register (register 31) . when the adj_srx bit is set, the switch node slew rate f or the channel is reduced , which in turn reduces high frequency spike noise. enabling this feature reduce s the efficiency of th e channel, however, due to increased switching losses. for this reason, use the slew rate adjustment feature only whe n low output noise is critical. forced pwm ( fpwm ) mode forced pulse - width modulation (f pwm) mode maintains pwm operation despite light load conditions, allowing negative current to flow from the inductor through the low - side switching fet. this mode is also referred t o as continuous conduction mode ( ccm ). the fpwm option has the lowest efficiency, but may be selected whe n constant frequency and low ripple are absolutely required , regardless of load. auto dcm auto matic d iscontinuous c onduction m ode (auto dcm ) is availab le on c hannel 5 and c hannel 6. auto dcm turns off the low - side switching fet when the inductor current falls to zero during the t off period , preventing negative current from flow ing through the low - side fet. this operation is equivalent to that of traditio nal flywheel diod e - based pwm regulators. auto dcm has higher efficiency than fpwm mode because negative inductor current is not allowed, but rather is re circulated to the input side. at very light loads in a uto dcm , some pulse skipping occur s and, therefor e, switching is not at a constant frequency. auto psm auto matic p ower s ave m ode ( auto psm ) is similar to a uto dcm , except that it intentionally turns on the high - side fet with a fixed period ( approx imately 80% of nominal t on ). this operation forces the reg ulator to skip a number of pwm cycles. compared to auto dcm, a uto psm skip s a larger number of cycles and begin s skip - ping cycles at a higher load current. auto psm reduces switching losses dramatically and improves efficiency , as shown in figure 44 . however, in light load conditions , larger output voltage ripple can be expected. figure 43 . auto psm, auto dcm, and fpwm operation ( s witch n ode and i nductor c urrent s hown, d ashed l ine i ndicate s 0 a ) figure 44 . efficiency of auto psm, auto dcm, and fpwm operation selecting l ight l oad s witching m odes each dc - to - dc converter channel can be configured with its own light load switching mode usin g the auto - psmx bits in register 28 and , for channel 5 and channel 6, the dcm56 bit in register 32 (see table 10 and table 11). table 10. light l oad s witching m odes , c hannel 1 to c hannel 4 auto - psm x bit l ight l oad s wi t ching m ode 0 fpwm 1 auto p sm table 11. light l oad s witching m odes , channel 5 and c hannel 6 auto - psm x bit dcm56 bit l ight l oad s wi t ching m ode 0 x 1 fpwm 1 0 auto p sm 1 1 auto dcm 1 x = dont care. au t o psm au t o dcm fpwm 1 1639-036 100 90 80 70 60 50 40 30 20 10 0 efficienc y (%) output current (a) 0.01 0.1 1 au t o psm au t o dcm fpwm 1 1639-037 rev. a | page 27 of 64
adp5080 data sheet s witching c lock the adp5080 integrates a highly accurate switching clock for the dc - to - dc converters and the charge pump. as shown in figure 45 , the internal clock can also be bypassed and the system synchro - nized to an external clock. w hen the internal clock source is used , the switching frequency for each dc - to - dc converter and the charge pump can be configur ed . figure 45 . switching clock distribution external sync h ronization mode when an external clock is present at the sync pin, all dc - to - dc converters and the charge pump automatically use it as their master switching clock ; the fr eq x bit settings in register 18 are ignored. when using external sync hronization mode, ensure that the external clock is already stable before the en signal is asserted to avoid unexpected behavior in the converters . when an external clock is used, the clo ck must operate within the specifications listed in table 1 . selecting the i nternal c lock f requency if the sync pin is tied high or low , the device uses the internal clock . the internal oscillator generates a maste r clock at either 2.0 mhz or 1.5 mhz , as specified by the sel_fsw bit in register 1 8 . the internal clock is active when en is high. the master c lock is divided down by half so that each dc - to - dc converter can select 1 or 1/2 the master clock frequency . t he frequency of each channel is set using the freq x bit (where x is 1 to 6) in register 18 . f o r example, if the master clock is set to 1.5 mhz , channel 1 through channel 6 can be configured to operate at 750 khz or 1.5 mhz , but not at 1 mhz or 2 mhz. for t he charge pump , the freq_cp bit s set the switching frequency (see the charge pump switching frequency section). selecting the external r esistor an external 100 k ? resist o r from the freq pin to gnd is required for the internal cloc k source oscillator. t o o btain a n a ccurate clock frequenc y, s elect a high precision resistor with a low temperature coefficient . a 1 nf bypass capacitor is also recommended at the freq pin. phase shifting each dc - to - dc converter can be configured to use t he inverted phase of the master clock by set ting the phase x bit (where x is 1 to 6) in register 20 . setting channels out of phase with each other helps reduce rms current stress on the input cap acitor s and spreads switching energy over two cycles. phase sh ifting reduces possible interference in a system due to propagated switching noise on the input rail. when any channel is operated at 1/2 f sw , the higher frequency channel must be set out of phase to have any effect on the apparent phase of the lower fre quency channel (see figure 46). figure 46 . switching phase relationships any channel at 1 f sw ha s the expected, set phase relationship to the master clock. however, when a channel opera tes at 1/2 f sw , it always appear s to be in phase with the master clock and with any in - phase channel at 1 f sw . this relationship is illustrated by the l ine s labeled 1 and 2 in figure 46; regardless of the phase setting , l ine 1 or line 2 is alw ays aligned to the rising edge. to set a channel operating at 1/2 f sw out of phase, the highest frequency channel must be set out of phase. referring to the l ine s labeled 3 in figu re 46 , the channel operating at 1/2 f sw is now out of phase with the channel operating at 1 f sw , regardless of the phase setting. clko pin the clock output (clko) pin can output the interna l switching clock used for c hannel 1. the output is enabled by setting the en_clko bit in register 19 to 1 . the clko output stays low when external clocking is used or when the en_clko bit is set to 0. ch1 ch2 freqx r osc 100k? freq clock source 2.0mhz (0) or 1.5mhz (1) sel_fsw sync sync detector charge pump 1/8 freq_cp[0] phasex en_clko clko sync detector 1/2 freq_cp[1] ch3 ch4 ch5 ch6 1/2 1 1639-039 in phase out of phase in phase out of phase master clock 2mhz 2 2 1 1 1mhz 1 1639-038 3 3 3 rev. a | page 28 of 64
data sheet adp5080 s oft s tart f unction t o provide controlled output voltage ramp ing on startup , t he adp5080 incorporates soft start control for each dc - to - dc con - verter. the ramp - up period to reach the target voltage can be set to 1 ms, 2 ms, 4 ms, or 8 ms using the ss x bit (where x is 1 to 6) in register 2 or register 3. the default soft start values are factory fuse programmed. it is not recommended that the adp5080 be started up into a full load condition. channel 7 : h igh voltage ldo regu lator the adp5080 integrates a high voltage ldo linear regulator , which allows input voltage s up to 25 v ( see figure 47). the ldo regulator outputs one of four preset regulated volt ages and is capable of providing up to 30 ma . figure 47 . high voltage ldo (channel 7) selecting the output voltage , channel 7 the o utput voltage of c hannel 7 is selected from one of the preset values ( 12 v, 9 v, 6 v , or 5 v ) usi ng the vid7 bits in register 16 . the default value is factory fuse programmed. discharge switch , channel 7 each channel incorporates a discharge switch . for channel 7, the discharge switch is located at the voldo7 pin. the dis - charge switch can be turned o n when channel 7 is turned o ff , removing the residual charge of the external capacitor via an internal 1 k? resist or. the discharge switch can be e nabled by setting the dscg 7_on bit in register 1. charge pump the adp5080 includes an integrated charge p ump , which provides power to the high - side swit ching nmos fet driver ( see figure 48). the charge pump raises the voltage applied to the pvincp pin by the vdr5 pin voltage, making the voltage available at the bstcp pin. in a typical application , the pvincp pin i s supplied by the battery (vbatt), and the vdr5 pin is supplied by vreg1 (5 v or 5.5 v). thus , the output voltage at the bstcp pin is vbatt + 5 v or 5.5 v, which is ideal for driv ing the high - side fet driver supply pin for each channel , bstx. figure 48 . charge pump for bstx supply the charge pump requires a minimum vbatt voltage to start up. in some cases , the start - up threshold, which is 4 v typical, may be higher than the rising uvlo threshold. if the bstcp voltage drops approxi mately 2.5 v below the nominal value , the adp5080 shuts down to prevent abnormal switching. an ovp or uvp fault is not indicated in this case. charge pump switching frequency the internal clock s ource generates either 2.0 mhz or 1.5 mhz , as set by the sel_fsw bit in register 18 . this master frequency is further divided by 1/2, 1/4, 1/8, or 1/16 by the freq_cp bits in register 19 (see table 53) . if the mast er clock frequency is set to 2.0 mhz, the charge pump switching clock frequency c an be 1.0 mhz, 500 khz, 250 khz, or 125 khz . if the master frequency is set to 1.5 mhz, the charge pump switching clock frequency can be 750 khz, 375 khz, 188 khz, or 94 khz. typically , a setting of 1/4 in 1.5 mhz operation or 1/8 in 2 mhz operation is recom - mended for the best efficiency. lower settings may not provide enough boost voltage when all channels are operating at load. if an external clock is used, the charge pump f requency can be set to 1/4 or 1/8 of the external frequency using the freq_cp bit s. charge pump efficiency is slightly affected by the duty cycle of the external clock ; a 50% duty cycle is the optimal point of operation. capacitor selection a 1 f capacito r is used for each charge p ump capacitor (c fly and c out ; see figure 48) . the voltage rating of these capacitors must be adequate for the charge - up voltage, that is, the p vincp pin voltage across c fly and the vdr5 p in voltage across c out . protection diode it is strongly recommended that a protection diode be mounted as shown in figure 48 to avoid problems during power - up while the bst cp voltage is charging. use a s chot t ky dio de that can withstand a 1 a peak current. programmable soft start power-good comparator uvp vref sequencer discharge switch 1 1639-040 adp5080 current limit current detection agnd vildo7 voldo7 up to 25v 5v to 12v agnd c+ c? pgnd5 pvincp bstcp vdr5 clock c fly 1 f c out 1f output v vbatt + v vdr5 vbatt bstx 1 1639-041 rev. a | page 29 of 64
adp5080 data sheet using the charge pump as the channel 7 input supply the charge pump can also be used to generate a high voltage for the channel 7 input. this configuration is enabled by adding the circuit shown in figure 49 in parallel with the bstx generating circuit shown in figure 48. figure 49 . charge pump used as a high voltage supply for channel 7 th e circuit shown in figure 49 gen erates vildo7 with the voltage v pvincp + 2 v v dr5 . i n a typical application , this voltage is equivalent to v v batt + 10 v to 11 v (pvincp = vbatt ; vdr5 = vreg1 = 5.5 v or 5 v). e nabling and d isabling the output c h annels each channel (channel 1 to channel 7) can be turn ed on and off using the s equencer m ode or the m anual m ode. a channel configured for s equencer m ode is automatically turn ed on and off by assertion and deasser tion of the en pin, with individually prog rammed delay times . a channel configured for m anual m ode does not automatically start when en goes high, but can be turned on or off via i 2 c control , as required. sequencer mode when the mode_en x bit ( x is 1 to 7) is set in register 29, the specified chann el turn s on and off under the control of the internal sequencer, which is triggered by the en pin (see figure 50) . when the en pin goes high, each channel controlled by the sequencer begins a soft start after the delay time specified by the en_dly x bits (see tabl e 23, table 25, table 27 , and table 29) . sim ilarly, when the en pin goes low, the channel turns off after the delay time specified by the dis_dly x bits ( see table 31, table 33, tabl e 35 , and table 37 ). note that figure 50 shows the logical states of each channel; it does not show soft start and discharge ramps. the disable delay time for all channels can be increased to four times its configured value by setting the dis_dly_extend bit in register 35 . when all channel s controlled by the sequencer are turned on, each channel can be manually turned off or on using the ch x _on bit ( x is 1 to 7 ) in register 48 . when the chx_on bit is used to turn a channel on or off, the enable state of the channel change s immediately , regardless of the settings of the en_dly x and dis_dly x bits . when using the sequencer mode, note the following: ? a channel that is controlled by the sequencer cannot be turned off m anually until after the sequencer turn s on all the channels that it controls and the soft start period has ended. this ready state can be identified by reading the pwrg x bits (x is 1 to 7) in regist er 24. ? after the en pin is asserted, writing to the vid x bits is forbidden while the internal sequencer is in operation to prevent unexpected behavior . the internal sequencer is in operation from the assertion of the en pin until the pwrg x bits in register 24 go high. manual mode when the mode_enx bit ( x is 1 to 7) is cleared in register 29, the specified channel turn s on and off under i 2 c control . all channels that are not configured for s equencer m ode can be manually turned on or off using the ch x _on bits ( x is 1 to 7 ) in the pctrl register (register 48) . writing 1 to the ch x _on bit enables the channel only when the en pin is logic high. when the en pin is taken low, all channels configured for m anual m ode turn off immediately , and all the ch x _on bits are reset to 0 . while the en pin is low, any data written to or read from the ch x _on bits is not valid. figure 50 . example power - up/power - down sequence using sequencer mode 1f 1 1639-042 vildo7 v pvincp + 2 v vdr5 bstcp c+ pvincp channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 t dis_dly1 en on on on on on on on off off off off off off off t dis_dly2 t dis_dly3 t dis_dly4 t dis_dly5 t dis_dly6 t dis_dly7 t en_dly1 t en_dly2 t en_dly3 t en_dly4 t en_dly5 t en_dly6 t en_dly7 1 1639-043 rev. a | page 30 of 64
data sheet adp5080 rev. a | page 31 of 64 en function the en pin has an internal pull-down resistor that holds the adp5080 in standby mode until the pin is actively pulled high. the en function does not take effect until the device is ready for operation, that is, until all the following conditions are met: ? vbatt pin voltage (v uvlo (batt) ) is above 3.3 v. ? vreg1 pin voltage is within the specified range. ? vreg2 pin voltage (v uvlo (por) ) is within the specified range. ? device is not in thermal shutdown. ? internal oscillator is stable (typically 250 s). ? pvin1 pin voltage (v uvlo (r) ) is above 3.7 v. ? vdr12 pin voltage is above 2.95 v. if any of these conditions are not met during operation, the adp5080 shuts down, as described in the uvlo and por section. en34 function the en34 pin allows channel 3, channel 4, or both channels to be independently enabled and disabled using the en34 pin. this functionality can be enabled on either or both channels using the dis_en34_chx bits (x is 3 or 4) in register 35. when the dis_en34_chx bit is set low, the channel is not turned on until both the en and en34 pins are high. if channel 3 or channel 4 is in sequencer mode, en34 must be high before en goes high to maintain the enable delay timing on the channels (see the sequencer mode section). if en is high when the en34 pin is taken high, channel 3 or channel 4 is immediately enabled or disabled, regardless of whether the channel is configured for manual mode or sequencer mode. when the dis_en34_chx bit is set high, channel 3 or channel 4 is enabled and disabled in the same way as all the other channels in the device, and the en34 pin has no effect on the operation of the channel. regardless of the state of the dis_en34_chx bits, disabling channel 3 and channel 4 does not cause fault to go low (see the fault function section). this means that the power-good flags for channel 3 and channel 4 do not need to be masked. fault goes low only when channel 3 or channel 4 is enabled using the ch3_on or ch4_on bit and the pwrg3 or pwrg4 bit subsequently goes low. power-good function the power-good status of each channel (pwrgx bit) can be read back from the pwrg register (register 24). a value of 1 for the pwrgx bit indicates that the regulated output voltage of channel x is within 85% to 125% of its nominal value. when the regulated output voltage of a channel falls below this level, the pwrgx bit is set to 0. as shown in figure 51, hysteresis is applied to both the upper and lower boundaries to minimize power-good chattering. figure 51. power-good status bit fault function the fault pin is an open-drain output that indicates the logical or status of the pwrgx bits for all channels. when any pwrgx bit = 0, the fault pin goes low. as shown in figure 52, fault has approximately 70 ms of blanking time after en is asserted to allow for the enable delay and soft start times. after the blanking period, a pwrgx low bit causes fault to go low immediately. fault remains low until the en pin is toggled or power is cycled. if an ovp or uvp condition at startup forces a shutdown before the fault blanking period ends, fault does not go low. figure 52. fault function if a channel is not enabled manually or via the sequencer, the pwrgx bit remains low. this forces fault low unless the channel is masked by the mask_pwrgx bit in register 25. this does not apply to channel 3 and channel 4, as described in the en34 function section. v out pwrgx (x = 1 to 7) 123% 85% 82% chx output 125% 11639-044 vbatt en fault reset reset timeout counter pwrgx 70ms 11639-045
adp5080 data sheet figure 53 . fault f unction l ogic d iagram table 12. channel 5 standalon e undervoltage d etection o ption sel_ind_uv5 bit undervoltage detected output any channel other than channel 5 channel 5 0 yes yes all channels shut down yes no all channels shut down no yes all channels shut down no no all channels are operationa l 1 yes yes all channels shut down yes no all channels shut down no yes channel 5 shuts down; all other channels are operational no no all channels are operational undervoltage protect ion (uvp) the adp5080 incorporates undervoltage protection (uvp) on c hannel 1 to c hannel 7 . w hen the output of any channel falls below 6 5 % of the specified voltage , uvp shuts down all seven channels by internally resetting the ch x _on bits in register 48. ch annel 5 can be configured for standalone undervoltage pro - tection (see the channel 5 standalone undervoltage detection o ption section) . uvp detection delay undervoltage detection includes a de bounce delay , which is configured in register 23 (see table 57) . the undervoltage condition is recognized only after it continue s for the period specified by the uv_dly bits in register 23 (see figure 54). setting the uv_dly bits to 11 disables uvp. figure 54 . undervoltage detection delay channel 5 standalone undervoltage d etection o ption if desired, undervoltage protection on channel 5 can be isolated fro m uvp on all the other channels. when the sel_ind_uv5 bit is set high in register 34, an undervoltage condition on channel 5 causes only channel 5 to be shut down (see table 12 ) . if this option is selected, the uv_ dly5 bit s in register 34 can be used to set a uvp detection delay for channel 5 only . pwrg1 pwrg2 pwrg5 pwrg6 pwrg7 d en timeout logic q 0 1 vbatt_uvlo r mask_pwrg1 mask_pwrg2 mask_pwrg3 mask_pwrg4 mask_pwrg5 mask_pwrg6 mask_pwrg7 pwrg3 ch3_on pwrg4 ch4_on 1 0 1 0 1 1639-046 fault v out chx_on (x = 1 to 7) uvx (x = 1 to 7) time 65% t < uv_dly shutdown t = uv_dly 1 1639-047 rev. a | page 32 of 64
data sheet adp5080 recovering from uvp after the cause of the undervoltage condition is removed, the outputs can be recovered by toggling en from low to high. if standalone c hannel 5 under voltage shutdown is enabled ( by setting the sel_ind_uv5 bit in register 34 ) , c hannel 5 can be recovered by setting the ch5_on bit in register 48 to 1 . the undervoltage status of a channel is stored in the uvpst register (register 26) after shutdown and ca n be read back from the uv x bit in register 26 . the uvx bit is cleared by writing a 1 to it. overvoltage protection (ovp) the adp5080 incorporates ov ervoltage protection (ovp) on c hannel 1 to c hannel 6 . w hen the output of any of these channels rises above 125 % of the specified voltage , ovp shuts down all six channels by internally resetting the ch x _on bits in register 48. ovp detection delay overvoltage detection includes a de bounce delay , which is configured in register 23 (see table 57) . the ov ervoltage condition is recognized only after it continue s for the period specified by the o v_dly bits in register 23 (see figure 55). setting the o v_dly bits to 11 disables o v p. recovering from ovp after the cause of the overvoltage condition is removed, the outputs can be recovered by toggling en from low to high . the overvoltage status of a channel i s stored in the o vpst register (register 27) after sh utdown and can be read back from the ov x bit in register 27 . the ovx bit is cleared by writing a 1 to it. figure 55 . overvoltage detection delay v out chx_on (x = 1 to 6) ovx (x = 1 to 6) time 125% t < ov_dly shutdown t = ov_dly 1 1639-048 rev. a | page 33 of 64
adp5080 data sheet a pplications informat ion this section provides component and pcb layout guid elines to ensure optimal device performance, efficiency, stability, and minimal switching noise an d crosstalk . component selection for the buck and buck b oost regulators setting the output voltage ( a djustable mode c hannels) channel 3, channel 4, and chann el 6 can be configured for an adjustable output voltage . table 9 provides the adjustable output voltage range for these channels. when any of these channels is configured for adjustable mode , connect a resistor div ider to the fb x pin between v out and gnd , as shown in figure 56. figure 56 . feedback resistors for adjustable output the resistor values can be calculated as follows, where 0.8 v is the typical fb voltage, and 20 k? is a good typical value for r fb_ bot . ( ) bot fb out top fb r v r ? = selecting the inductor the required inductor value can be determined by the input and output voltages, the switc hing frequency, and the ripple current, as shown in e quation 1. in out sw ripple out in v v f i v v l ? = 1 (1) where: l is the inductor value . f sw is the switching frequency . i ripple is a peak - to - peak value for the ripple current . in general, the recommended ripple current i s 30% of the maxi - mum load current . therefore, equation 1 can be rewritten as follows: in out sw load out in v v f i v v l ? = 1 3 . 0 (2) note that ripple current var ies with input voltage. the typical input voltage can be used to determine the inductor value . h owever , to avoid inducto r saturation and current limi t, also calculate t he inductor value with the worst - case input voltage (v in max ) . the maximum rated current of the selected inductor (both rms current and saturation current ) must be greater than the peak inductor curren t (i peak ) at the maximum load current. if the rating of the inductor is not sufficient , the inductor may saturate due to inductor value degradation, causing it to reach the current limit, even in a lower load condition than expected. the peak current can b e estimated using equation 3. i peak = i load + ( i ripple /2) (3) if the 30% ripple guideline is followed, typical peak current is simplified as follows: i peak = ( i load + 0.15 ) i load = 1.15 i load (4) an other important specification to consider is the paras itic series resistance in the inductor: dc resistance (dcr). a larger dcr decrease s efficiency, but a larger size inductor typically has lower d cr . t herefore, the trade - off between available space on the pcb and device performance must be considered carefu lly. e quation 1 to e quation 4 apply to the buck regulators. although channel 6 is a buck boost regulator , the inductor value can be determined using the buck regulator mode of operation given that the available step - up ratio in boost mode is relatively sma ll (4 v at the pvin6 pin to 5.5 v at the vout6 pin ) compared to the available step - down ratio. therefore , an inductor value selected for buck regulator mode typically w ork s equally well in boost regulator mode. table 13 lists reco mmended inductor values for a range of volt - ages and frequencies. the values provided are based on a wide operating range and assume the maximum load current for each channel. in the actual application , larger or smaller values may be more appropriate . in general, the inductor value can be increased or decreased by one standard value from the recommended 30% ripple guideline. a larger inductance provide s higher efficiency, wh ereas smaller values result s in better transient response and a smaller footprint. note that inductor values much smaller or larger than the ones recommended in table 13 may cause control loop instability. it is also important to note that because the current - limit pro - tection monitors peak or v alley current, the selected inductance affect s the load current level at which current limit is triggered. v out fbx r fb_ t op r fb_bot 1 1639-052 rev. a | page 34 of 64
data sheet adp5080 table 13 . suggested inductors channel v out (v) frequency ( k hz) inductance ( h) part n umber 1 <1 .0 750 or 1000 1 toko fd sd0420 -h - 1r0 1500 or 2000 0.47 toko fdsd0420 -h - r47 1.0 to 1 .2 750 or 1000 1.5 toko fdsd0420 -h - 1r5 1500 or 2000 0.68 toko fdsd0420 -h - r68 2 < 1.8 750 or 1000 4.7 toko fdsd0420 -h - 4r7 1500 or 2000 2.2 toko fdsd0420 -h - 2r2 1.8 to 3.3 750 or 1000 6.8 taiyo yuden nrs4018t6r8m 1500 or 2000 3.3 toko fdsd0420 -h - 3r3 3 < 1.5 750 or 1000 3.3 toko fdsd0420 -h - 3r3 1500 or 2000 1.5 toko fdsd0420 - h - 1r5 1.5 to 1.8 750 or 1000 3.3 toko fdsd0420 -h - 3r3 1500 or 2000 1.5 toko fdsd0420 -h - 1r5 4 < 2.5 750 or 1000 6.8 taiyo yuden nrs4018t6r8m 1500 or 2000 3.3 toko fdsd0420 -h - 3r3 2.5 to 3.55 750 or 1000 10 taiyo yuden nrs4018t100m 1500 or 2000 4.7 toko fdsd0420 -h - 4r7 5 < 4 750 or 1000 3.3 toko fdsd0420 -h - 3r3 1500 or 2000 2.2 toko fdsd0420 -h - 2r2 4 to 5 750 or 1000 3.3 toko fdsd0420 -h - 3r3 1500 or 2000 1.5 toko fdsd0420 -h - 1r5 6 < 4.5 750 or 1000 4.7 toko fdsd0420 -h - 4r7 1500 or 2000 2.2 toko fdsd0420 -h - 2r2 4.5 to 5.5 750 or 1000 4.7 toko fdsd0420 -h - 4r7 1500 or 2000 3.3 toko fdsd0420 -h - 3r3 sel ecting the input capacitor step - down switching regulators draw current from the input supply in pulses that have very fast rise and fall times. low esr ceramic input capacitor s are required to reduce the input voltage ripple and provide bypass for high fre quency switching noise. if not well bypassed, the input noise can cause poor device perfor - mance, instability, and increased conducted and radiated emissions (emi). each switching channel should have approximately 10 f of input bypass capacitance. place t he input cap acitor s as close as possible to the pvinx and pgndx pins. place a n additional ceramic input capacitor at vbatt. it is usually beneficial to use multiple cap acitor s in parallel instead of a single high value capacitor. note that ceramic capacit ors have very strong dc bias character - istics and lose as much as 80% of their capacitance value at the rated voltage. also , note that the rise in case temperature due to rms current in the input capacitor can be quite high on the input of a buck regulator . for these reasons, capacitors of x5r and x 7r type or better are recommended. a good estimate for the rms current in the input c apacitor of a single channel is in out in out load rms v v v v i i ) ( ? = selecting the output capacitor the output capacitor is important for re gulator operation because it affects the loop stabilit y, output voltage ripple , and load transient response. the adp5080 is designed to operate with low esr ceramic output capacitors. higher outp ut capacitor values reduce the output voltage ripple and improve l oad t ransient step response. when choosing an output capacitor value, it is also important to account for the loss of capacitance due to output voltage dc bias. table 14 lists t he minimum recommended capacitor values for each channel. note that the capacitor values shown in tabl e 14 are n ominal values, not de rated values. the capacitors listed work for the ful l range of operating frequency and load . l ower values can be used at higher frequency or lighter load currents. however, exercise caution when using values smaller than the minimum recommended values; too small an output capacitor can result in unstable o peration. output capacitance can typically be increased with no practical limit without causing stability problems. greater capacitance improve s ri pple and transient performance. rev. a | page 35 of 64
adp5080 data sheet table 14 . minimum recommended output capacitors ch annel output capacitor ( f) 1 44 2 44 3 44 4 33 5 44 6 44 ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. capacitors must have a dielectric that is adequate to ens ure the minimum capacitance over the necessary temperature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of at least 2 v out are re commended for best performance. the peak - to - peak output voltage ripple for the selected output capacitor and inductor values is calculated using equation 5 . v ripple = out sw ripple out sw in c f i c l f v = 8 2 ) 2 ( (5) high esr c apacitors are not recommended because they increase output ripple and can cause loop instability. e quation 5 assumes ceramic capacitors and does not include esr. f o r optimal performance, place output capacitors to minimize pcb parasitics. connect capacitor pads directly to the output and gnd power paths, not via separate traces. for purposes of high frequency noise reduction , it can be beneficial to use multiple capacitors in parallel instead of a single high value capacitor. because c h annel 6 operates in buck boost mode, the output capacitor s see large switching currents. therefore, placement of the output capacitor s requires additional attention. make sure to place the output capacitors as close as possible to the v out 6 and pgnd 6 pins of c h annel 6. component selection for the ldo regulator s selecting the capacitor s use l ow esr capacitors fo r all ldo input and output capacitors. lower esr reduces t he output impedance and ripple voltage . high esr capacitors are not recommended due to ripple and stability of the ldo control loop . t herefore, it is recommended that surface - mount ceramic capacitor s be used. the x5r and x7r type of capacitor is preferable for adequate performance. use an output capacitor with a value from 2.2 f to 10 f for vreg2 . v alues of 4.7 f to 10 f are recommended for vreg1 ; 4.7 f is the min imum requirement for stability. for the channel 7 high voltage ldo regulator , the minimum required output capacitor value for the voldo7 pin is 1 f. because channel 7 is a high voltage output, make sure to account for capacitor bias voltage derating. if the charge pump doubler circuit is used as the input supply to channel 7, the maximum reco mmended value for the channel 7 output capacitor is 3.3 f. this is to prevent overloading the charge pump during startup. pcb layout recommend ations proper printed circuit board (pcb) layout is essential for optimal device performance and thermal dissipat ion, and to minimize switching n oise and electromagnetic interf eren ce (emi). a few key layout guideline s are provided in the following sections . sensitive signal treatment it is important to isolate sensitive signal trace s from noisy switching trace s . t he fb x pins and the freq pin are sensitive to noise coupling and should be routed away from noise sources. any node with high dv/dt such as swx, bstx, and scl is considered a noise source . additional noisy circuit areas to avoid are the main areas of high swi tching current: primarily the input capacitors and pgndx connections . finally, do not rout e sensitive nodes below or near the inductors. if a sensitive signal trace must cross a noisy source, it is recommended that at least one pcb ground layer be placed b etween these signal trace s as a shield. grounding i t is recommended that the analog ground ( a gnd) and power ground (pgnd) planes be separate d . t he a gnd plane is used for the device reference voltage ; therefore, it should be as quiet as possible and not use d as a current path. the pgnd plane serves as the current return path for the regulators . pgnd can be very noisy due to the flow of current , as well as the presence of switch - ing noise. therefore, care must be taken with the connection of the a gnd and pgn d planes so that currents flowing in the pgnd plane do not intrude on the agnd region. connect t he agnd and pgnd planes at a single point, preferably at the device . the pgndx nodes are part of the regulation loop for each switching regulator and carry fast switching currents. therefore , i t is critical that the pgndx regions for each switching regulator be separated and connected to the pgnd plane at the output capacitor groun d . t his prevents interference from adjacent channels and helps contain switching no ise. multiple vias are recommended for the connection between the pgndx regions and the pgnd plane. to improve thermal performance and noise immunity, each agnd or pgnd layer should have as much copper coverage as possible. rev. a | page 36 of 64
data sheet adp5080 external component plac ement and signal routing the majority of the critical switching regulat or pins are located on the outer bumps of the device, making it easier to lay o ut and connect to the external components. in general, make t race s that handle large current as wide and s hort as possible . this consid - eration appli es to the traces for pvinx, swxa , swx b, swx , pgndx, and vout 6 . make t races that handle switching currents as short as possible. these critical areas are pvinx, sw6b, vout6, and pgndx. r educing the trace length on these nodes helps mitigate noise coupling. f o r these connections, avoid using vias because they add parasitic inductance in the current path. i f vias are required due to routing restriction s , place multiple vias in parallel. for the buck regulators , the in put capacitor has placement priority. place t he input capacitor as close as possible to the pvinx and pgndx pins with wide trace connections. f o r channel 6 , the critical component connections are the input capacitor and the out put capacitor . connect these components as close as possible to the p vin 6 , vout 6 , and pgnd 6 pins. f o r all channels , keep the swx pin to inductor connection as short as possible to minimize capacitive coupling . because the swx nodes carr y high current , the traces must be wide enough to handle it. thermal consideratio n s the adp5080 is a high efficiency power converter . h owever, in applications with heavy loads at high ambient temperature (t a ), the heat dissipated on the device may exceed the maximum junction temperature of 125 c . if the junction temperature (t j ) exceeds 16 5 c , the adp5080 enters thermal shutdown (tsd), and all outputs are disabled. when the junction te mperature falls below approximately 1 50c , tsd is cleared. after a tsd event, the adp5080 does not rest art automatically , but must be re enabled with the en pin. the junction temperature can be ca lculated using e quation 6. t j = t a + t r ( 6) where t r is the rise in junction temperature of t he device due to power dissipation. t he rise in junction temperature is directly proportional to the power dissipation in the device , as shown in e quation 7. t r = p d loss ja (7) where: pd loss is the power dissipation in the adp5080 . ja is the junction - to - ambient thermal resistance of the package mounted on a pcb . the ja value provided in table 7 is for a jedec standard board. however, this value is only a benchmark and does not necessarily correlate to th e thermal performance of a real - world pcb . the thermal performance of the wlcsp package itself is given by the jb value (see table 7 ) . this value is the thermal resistance from junction to solder ball and varies little with pcb design. t o determine the junction temperature, it is recommended that the adp5080 case temperature be measured under wors t - case condition s. t he case temperature (t c ) is defined as the temper - ature on the top surface of the device and can be calculated using e quation 8. t c = t a + p d loss ( ja ? jc ) ( 8 ) where: jc is the junction - to - case thermal resistance of the package, which is 0.2 c / w. because jc is very low , it can be seen from e quation 9 that the measured value of t c is a good approximation of t j . t j = t c + t r = t c + p d loss jc t c (9) t he estimated junction temperature or measured case tempera - ture in worst - case conditions must be less than the maximum junction temperature of 125 c . rev. a | page 37 of 64
adp5080 data sheet i 2 c interface the adp5080 incl udes an i 2 c - compatible serial interface to control the power management blocks and to read back system status. the i 2 c serial interface provides access to the internal registers o f the adp5080 . f or detailed information about the registers, s ee the control register information section . all registers programmed by the i 2 c interface are cleared and reset to their default values by a power - on reset (see the power - on reset (por) section). the chx_on bits in the pctrl register ( register 48 ) are cleared by a power - on reset or by taking the en pin low. the i 2 c interface operates at clock frequencies of up to 400 khz. t he adp5080 does not respond to general calls. the adp5080 accepts multiple masters, but if the device is in read mode, access is limited to one master until the data transmission is completed. sda and scl pins the adp5080 has two dedicated i 2 c pins : sda and scl. sda is an open - drain line for receiving and transmitting data. scl is a n input line for receiving the clock signal. these buses must be externally pulled up to the vddio supply . serial data is transferred by the scl rising edge. the read data is generated at the sda pin in read mode. if the v vddio voltage level is below the u ndervoltage threshold (typically 950 mv ) , the en signal goes low , and the sda and scl pins are left hi gh - z. t he internal level shifter is disabled to prevent corrupt data from being received. note that t he scl pin must be pull ed high to vddio during power - up so that the programmed fuse settings ar e properly loaded into the i 2 c registers at power - on reset (por) . this restriction does not apply as long as vddio is low. if vddio is supplied by vreg2, scl must be high impedance until vreg2 rises above the por threshold. if vddio is supplied by an external i 2 c host, either scl must be held high or the vddio supply must be off until the vreg 2 voltage rises above the por threshold. i 2 c address the 7 - bit i 2 c chip address for the adp5080 is 0x 3 0 (011 0000) ; the subaddress is used to select one of the user registers , through which the i 2 c master communicates with the adp5080 . self - clear ing register bit s register 26 and register 27 are status registers that contain self - clear ing register bit s. these bit are cleared automatically when a 1 is written to the status bit. therefore, it is not necessary to write a 0 to the status bit to clear it. i 2 c inte rface timing diagrams figure 57 is a timing diagram for the i 2 c write operation. figure 58 and figure 59 are timing diagrams for the i 2 c read operation. register 48 ( pctrl register ) has a special status flag in bit 7 that indicates the presence of valid data in th is register (see figure 59) . if bit 7 = 0, the data is not yet valid, and the r ead operation must be repeated until the status bit changes to 1 . figure 57 . i 2 c write to registers figure 58 . i 2 c read from registers with no read status bit (all registers except pctrl) scl chip address sda a0 a1 a2 a3 a4 a5 a6 a0 a1 a2 a3 a4 a5 a6 a7 0 0 0 0 0 1 1 0 d0 d1 d2 d3 d4 d5 d6 d7 subaddress write data ack by slave write start ack by slave ack by slave r/w stop notes 1. maximum scl frequency is 400khz. 2. no response to general call. output by processor output by adp5080 1 1639-049 scl chip address sda a0 a1 a2 a3 a4 a5 a6 a0 a1 a2 a3 a4 a5 a6 a7 0 0 0 0 0 1 1 0 1 0 0 0 0 1 1 0 d0 d1 d2 d3 d4 d5 d6 d7 subaddress chip address read data notes 1. maximum scl frequency is 400khz. 2. no response to general call. output by processor output by adp5080 ack by slave repeated start write start ack by slave read ack by slave no ack by master to stop reading r/w a0 a1 a2 a3 a4 a5 a6 r/w stop 1 1639-050 rev. a | page 38 of 64
data sheet adp5080 figure 59 . i 2 c read from register with read status bit (pctrl register) scl chip address sda a0 a1 a2 a3 a4 a5 a6 a0 a1 a2 a3 a4 a5 a6 a7 0 0 0 0 0 1 1 0 1 1 0 0 0 0 1 1 0 d0 d1 d2 d3 d4 d5 d6 d7 subaddress chip address read data read data notes 1. maximum scl frequency is 400khz. 2. no response to general call. output by processor output by adp5080 ack by slave write start ack by slave repeated start read read status ack by slave ack by master to continue reading no ack by master to stop reading r/w a0 a1 a2 a3 a4 a5 a6 r/w stop d0 d1 d2 d3 d4 d5 d6 1 1639-051 rev. a | page 39 of 64
adp5080 data sheet control register information control register map table 15 lists all control registers for the adp5080 . any bits shown as blank are reserved. table 15 . control register map register address register name reg. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0x00 reserved reserved 1 0x01 dscg dscg 7 _on dscg 6 _on dscg 5 _on dscg 4 _on dscg3_on dscg2_on dscg1_on 2 0x02 sfttim1234 ss4[1:0] ss3[1:0] ss2[1:0] ss1[1:0] 3 0x03 sfttim567 ss7 ss6 [1:0] ss5 [1:0] 4 0x04 en_dly12 en_dly2 [ 2 :0] en_dly1 [ 2 :0] 5 0x05 en_dly34 en_dly4 [ 2 :0] en_dly3 [ 2 :0] 6 0x 06 en_dly56 en_dly6 [ 2 :0] en_dly5 [ 2 :0] 7 0x07 en_dly7 en_dly7 [ 2 :0] 8 0x08 dis_dly12 dis_dly2 [ 2 :0] dis_dly1 [ 2 :0] 9 0x09 dis_dly34 dis_dly4 [ 2 :0] dis_dly3 [ 2 :0] 10 0x0a dis_dly56 dis_dly6 [ 2 :0] dis_dly5 [ 2 :0] 11 0x0b dis_dly7 dis_dly7 [ 2 :0] 12 0x0c vid1 vid1 [ 4 :0] 13 0x0d vid23 vid3 [ 2 :0] vid2 [ 3 :0] 14 0x0e vid45 vid5 [ 2 :0] vid4 [ 2 :0] 15 0x0f vid6 vid6 [ 3 :0] 16 0x10 vid7_ldo12 vid_ldo2 [ 1 :0] vid_ldo1 vid7 [ 1 :0] 17 0x11 dvs12 dvs2_intvl dvs1_intvl en_dvs2 en_dvs1 18 0x12 sel_fr eq sel_fsw freq6 freq5 freq4 freq3 freq2 freq1 19 0x13 sel_freq_cp en_clko freq_cp[1:0] 20 0x14 sel_phase phase6 phase5 phase4 phase3 phase2 phase1 23 0x17 prot_dly uv_dly[1:0] ov_dly[1:0] 24 0x18 pwrg en pwrg7 pwrg6 pwrg5 pwrg4 pwrg3 pwrg2 pwrg1 25 0x19 mask_pwrg mask_ pwrg7 mask_ pwrg6 mask_ pwrg5 mask_ pwrg4 mask_ pwrg3 mask_ pwrg2 mask_ pwrg1 26 0x1a uvpst uv7 uv6 uv5 uv4 uv3 uv2 uv1 27 0x1b ovpst ov6 ov5 ov4 ov3 ov2 ov1 28 0x1c auto - psm a uto - psm6 a uto - psm5 a uto - psm4 a uto - psm3 a uto - psm2 a uto - psm1 29 0x1d seq_mode mode_en7 mode_en6 mode_en5 mode_en4 mode_en3 mode_en2 mode_en1 30 0x1e adj_bst_vth6 buck6_only boost6_vth[1:0] 31 0x1f opt_sr_adj a dj_sr6 a dj_sr5 a dj_sr4 a dj_sr3 a dj_sr2 a dj_sr 1 32 0x20 dcm 56 _gscal1 dcm56 gate_scal1 33 0x21 sel_inp_ldo12 sel_inp_ ldo2 sel_inp_ ldo1 34 0x22 sel_ind_uv5 uv_dly5[1:0] sel_ind_ uv5 35 0x23 option_sel reduce_ vout1 dis_dly_ extend dis_en34_ ch4 dis_en34_ ch 3 48 0x3 0 pctrl rdst_pctrl ch7_on ch6_on ch5_on ch4 _on ch3_on ch2_on ch1_on rev. a | page 40 of 64
data sheet adp5080 control register det ails this section describes the bit functions of each register used by the adp5080 . register 1: dscg (discharge switch control) , address 0x01 r egister 1 disables and enables the discharge switch for channel 1 to channel 7 . t he default values are defined by the fuse option. table 16. register 1 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dscg7_on dscg6 _on dscg5_on dscg4_on dscg3_on dscg2_on dscg1_on table 17. dscg register, bit function description s bits bit name access description 6 dscg 7 _on r/w 0 = disable output discharge switch for channel 7. 1 = enable output discharge sw itch for channel 7. 5 dscg 6 _on r/w 0 = disable output discharge switch for channel 6. 1 = enable output discharge switch for channel 6. 4 dscg 5 _on r/w 0 = disable output discharge switch for channel 5 . 1 = enable output discharge switch for channel 5. 3 dscg 4 _on r/w 0 = disable output discharge switch for channel 4. 1 = enable output discharge switch for channel 4. 2 dscg 3 _on r/w 0 = disable output discharge switch for channel 3. 1 = enable output discharge switch for channel 3. 1 dscg 2 _on r/w 0 = disa ble output discharge switch for channel 2. 1 = enable output discharge switch for channel 2. 0 dscg 1 _on r/w 0 = disable output discharge switch for channel 1. 1 = enable output discharge switch for channel 1. register 2: sfttim 1234 (soft start time for channel 1 , channel 2, channel 3 , and channel 4 ) , address 0x0 2 r egister 2 sets the soft start time for channel 1 to channel 4 . t he default values are defined by the fuse option. table 18. register 2 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ss4 ss3 ss2 ss1 table 19. sfttim1234 register, bit function description s bits bit name access description [7:6] ss4 r/w soft start time for channel 4. 00 = 1 ms . 01 = 2 ms . 10 = 4 ms . 11 = 8 ms . [ 5:4] ss3 r/w soft start time for channel 3. 00 = 1 ms . 01 = 2 ms . 10 = 4 ms . 11 = 8 ms . [3:2] ss2 r/w soft start time for channel 2. 00 = 1 ms . 01 = 2 ms . 10 = 4 ms . 11 = 8 ms . [1:0] ss1 r/w soft start time for channel 1. 00 = 1 ms . 01 = 2 ms . 10 = 4 ms . 11 = 8 ms . rev. a | page 41 of 64
adp5080 data sheet register 3: sfttim 567 (soft start time for channel 5 , channel 6 , and channel 7 ) , address 0x0 3 r egister 3 sets the soft start time for channel 5 to channel 7 . t he default values are defined by the fuse option. table 20. register 3 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ss7 ss6 ss5 table 21. sfttim567 register, bit function description s bits bit name access description 4 ss7 r/w soft start time for channel 7. 0 = 2 ms . 1 = 4 ms . [3:2] ss6 r/w soft start time for channel 6. 00 = 1 ms . 01 = 2 ms . 10 = 4 ms . 11 = 8 ms . [1:0] ss5 r/w soft start time for channel 5. 00 = 1 ms . 01 = 2 ms . 10 = 4 ms . 11 = 8 ms . register 4: en_dly 12 (enable delay time for channel 1 and chan nel 2 ) , address 0x0 4 r egister 4 sets the enable delay time for channel 1 and channel 2 . t he default values are defined by the fuse option. table 22. register 4 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 en_dly 2 en_dly1 table 23. en_dly12 register, bit function description s bits bit name access description [6:4] en_dly2 r/w enable delay time for channel 2. 000 = 0 ms . 001 = 2 ms . 010 = 4 ms . 011 = 6 ms . 100 = 8 ms . 101 = 10 ms . 110 = 12 ms . 111 = 14 ms . [ 2:0] en_dly1 r/w enable delay time for channel 1. 000 = 0 ms . 001 = 2 ms . 010 = 4 ms . 011 = 6 ms . 100 = 8 ms . 101 = 10 ms . 110 = 12 ms . 111 = 14 ms . rev. a | page 42 of 64
data sheet adp5080 register 5: en_dly 34 (enable delay time for channel 3 and channel 4 ) , address 0x0 5 r egister 5 sets the enable delay time for channel 3 and channel 4 . t he default values are defined by the fuse option. table 24. register 5 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 en_dly4 en_dly3 table 25. en_dly34 register, bit function description s bits bit name access description [6:4] en_dly4 r/w enable delay time for channel 4. 000 = 0 ms . 001 = 2 ms . 010 = 4 ms . 011 = 6 ms . 100 = 8 ms . 101 = 10 ms . 110 = 12 ms . 111 = 14 ms . [2:0] en_dly3 r/w enable delay time for channel 3. 000 = 0 ms . 001 = 2 ms . 010 = 4 ms . 011 = 6 ms . 100 = 8 ms . 101 = 10 ms . 110 = 12 ms . 111 = 14 ms . register 6: en_dly 56 (enable delay time for channel 5 and channel 6 ) , address 0x0 6 r egister 6 sets the enable delay time for channel 5 and channel 6 . t he default values are defined by the fuse option. table 26. register 6 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 en_dly6 en_dly5 table 27. en_dly56 register, bit function description s bits bit name access description [6:4] en_dly6 r/w enable delay time for channel 6. 000 = 0 ms . 001 = 2 ms . 010 = 4 ms . 011 = 6 ms . 100 = 8 ms . 101 = 10 ms . 110 = 12 ms . 111 = 14 ms . [2:0] en_dly5 r/w e nable delay time for channel 5. 000 = 0 ms . 001 = 2 ms . 010 = 4 ms . 011 = 6 ms . 100 = 8 ms . 101 = 10 ms . 110 = 12 ms . 111 = 14 ms . rev. a | page 43 of 64
adp5080 data sheet register 7: en_dly 7 (enable delay time for channel 7 ) , address 0x0 7 r egister 7 sets the enable delay time for channel 7 . t h e default value i s defined by the fuse option. table 28. register 7 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 en_dly7 table 29. en_dly7 register, bit function description s bits b it name access description [2:0] en_dly 7 r/w enable delay time for channel 7. 000 = 0 ms . 001 = 2 ms . 010 = 4 ms . 011 = 6 ms . 100 = 8 ms . 101 = 10 ms . 110 = 12 ms . 111 = 14 ms . register 8: dis _dly 12 ( dis able delay time for channel 1 and channel 2 ) , addr ess 0x0 8 r egister 8 sets the disable delay time for channel 1 and channel 2 . the disable delay depends on the setting of the dis_dly_extend bit in register 35 (bit 2 in address 0x23). t he default values are defined by the fuse option. table 30. register 8 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dis_dly2 dis_dly1 table 31. dis_dly12 register, bit function description s bits bit name r/w description [ 6:4] dis_dly2 r/w these bits set the disable delay time for channel 2. bits[6: 4 ] dis_dly_extend = 0 dis_dly_extend = 1 000 0 ms 0 ms 001 4 ms 16 ms 010 8 ms 32 ms 011 12 ms 48 ms 100 16 ms 64 ms 101 20 ms 80 ms 110 24 ms 96 ms 111 28 ms 112 ms [ 2:0] di s_dly1 r/w these bits set the disable delay time for channel 1. bits[2:0] dis_dly_extend = 0 dis_dly_extend = 1 000 0 ms 0 ms 001 4 ms 16 ms 010 8 ms 32 ms 011 12 ms 48 ms 100 16 ms 64 ms 101 20 ms 80 ms 110 24 ms 96 ms 111 28 ms 112 ms rev. a | page 44 of 64
data sheet adp5080 register 9: dis _dly 34 ( dis able delay time for channel 3 and channel 4 ) , address 0x0 9 r egister 9 sets the disable delay time for channel 3 and channel 4 . the disable delay depends on the setting of the dis_dly_extend bit in register 35 ( bit 2 in address 0x23). t he default values are defined by the fuse option. table 32. register 9 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dis_dly4 dis_dly3 table 33. dis_dly34 regis ter, bit function description s bits bit name r/w description [ 6:4] dis_dly4 r/w these bits set the disable delay time for channel 4. bits[6: 4 ] dis_dly_extend = 0 dis_dly_extend = 1 000 0 ms 0 ms 001 4 ms 16 ms 010 8 ms 32 ms 011 12 ms 48 ms 100 16 ms 64 ms 101 20 ms 80 ms 110 24 ms 96 ms 111 28 ms 112 ms [ 2:0] dis_dly3 r/w these bits set the disable delay time for channel 3. bits[2:0] dis_dly_extend = 0 dis_dly_extend = 1 000 0 ms 0 ms 001 4 ms 16 ms 010 8 ms 32 ms 011 12 ms 48 ms 100 16 ms 64 ms 101 20 ms 80 ms 110 24 ms 96 ms 111 28 ms 112 ms rev. a | page 45 of 64
adp5080 data sheet register 10: dis _dly 56 ( dis able delay time for channel 5 and channel 6 ) , address 0x0 a r egister 10 sets the disable delay time for channel 5 and channel 6 . the disable delay depends on the setting of the dis_dly_extend bit in register 35 (bit 2 in address 0x23). t he default values are defined by the fuse option. table 34. register 10 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dis_dly6 dis_dly5 table 35. dis_dly56 register, bit function description s bits bit name r/w description [ 6:4] dis_dly6 r/w these bits set the disable delay time for channel 6. bits [6: 4 ] dis_dly_extend = 0 dis_dly_extend = 1 000 0 ms 0 ms 001 4 ms 16 ms 010 8 ms 32 ms 011 12 ms 48 ms 100 16 ms 64 ms 101 20 ms 80 ms 110 24 ms 96 ms 111 28 ms 112 ms [ 2:0] dis_dly5 r/w these bits set the disable delay ti me for channel 5. bits[2:0] dis_dly_extend = 0 dis_dly_extend = 1 000 0 ms 0 ms 001 4 ms 16 ms 010 8 ms 32 ms 011 12 ms 48 ms 100 16 ms 64 ms 101 20 ms 80 ms 110 24 ms 96 ms 111 28 ms 112 ms register 11: dis _dly 7 ( dis a ble delay time for channel 7 ) , address 0x0 b register 11 sets the disable delay time for channel 7 . the disable delay depends on the setting of the dis_dly_extend bit in register 35 (bit 2 in address 0x23). t he default value i s defined by the fuse option. t able 36. register 11 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dis_dly7 table 37. dis_dly7 register, bit function description s bits bit name r/w description [ 2:0] dis_dly7 r/w t hese bits set the disable delay time for channel 7. bits[2:0] dis_dly_extend = 0 dis_dly_extend = 1 000 0 ms 0 ms 001 4 ms 16 ms 010 8 ms 32 ms 011 12 ms 48 ms 100 16 ms 64 ms 101 20 ms 80 ms 110 24 ms 96 ms 111 28 ms 11 2 ms rev. a | page 46 of 64
data sheet adp5080 register 12: vid1 ( output voltage for channel 1 ) , address 0x0 c register 12 sets the output voltage for channel 1. the output voltage depends on the setting of the reduce_vout1 bit in register 35 (bit 3 in address 0x23). t he default value i s defined by the fuse option. table 38. register 12 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vid1 table 39. vid1 register, bit function description s bits bit name r/w description [ 4:0] vid 1 r/w these bits set the output voltage for channel 1. bits[ 4 :0] reduce_vout1 = 0 reduce_vout1 = 1 00000 1.20 v 1.11 v 00001 1.19 v 1.10 v 00010 1.18 v 1.09 v 00011 1.17 v 1.08 v 00100 1.16 v 1.07 v 00101 1.15 v 1.06 v 00110 1.14 v 1.05 v 00111 1.13 v 1.04 v 01000 1.12 v 1.03 v 01001 1.11 v 1.02 v 01010 1.10 v 1.01 v 01011 1.09 v 1.00 v 01100 1.08 v 0.99 v 01101 1.07 v 0.98 v 01110 1.06 v 0.97 v 01111 1.05 v 0.96 v 10000 1.04 v 0.95 v 10001 1.03 v 0.94 v 10010 1.02 v 0.93 v 10011 1.01 v 0.92 v 10100 1.00 v 0.91 v 10101 0.99 v 0.90 v 10110 0.98 v 0.89 v 10111 0.97 v 0.88 v 11000 0.96 v 0.87 v 11001 0.95 v 0.86 v 11010 0.94 v 0.85 v 11011 0.93 v 0.84 v 11100 0.92 v 0.83 v 11101 0.91 v 0.82 v 11110 0.90 v 0.81 v 11111 0.89 v 0.80 v rev. a | page 47 of 64
adp5080 data sheet register 13: vid23 ( output voltage for channel 2 and channel 3 ) , address 0x0 d r egister 13 sets the output voltage for channel 2 and channel 3 . t he default values are defined by the fuse option. table 40. register 13 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vid3 vid2 table 41. vid23 register, bit function description s bits bit name access description [6:4] vid3 r/w these bits set the output voltage for channel 3. 000 = 1.8 v. 001 = 1.5 v. 010 = 1.35 v. 011 = 1.3 v. 100 = 1.25 v. 101 = 1.225 v. 110 = 1.2 v. 111 = adjustable mode. [3:0] vid2 r/w these bits set the output voltag e for channel 2. 0000 = 3.3 v . 0001 = 3.2 v . 0010 = 3.15 v . 0011 = 3.00 v . 0100 = 1.8 v . 0101 = 1 .25 v . 0110 = 1.225 v . 0111 = 1 .2 v . 1000 = 1.175 v. 1001 = 1.15 v. 1010 = 1.125 v. 1011 = 1.1 v. 1100 = 1.075 v. 1101 = 1.05 v. 1110 = 1.025 v. 1111 = 1.0 v. rev. a | page 48 of 64
data sheet adp5080 register 14: vid45 ( output voltage for channel 4 and channel 5 ) , address 0x0 e r egister 14 sets the output voltage for channel 4 and channel 5 . t he default values are defined by the fuse option. table 42. register 14 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vid5 vid4 table 43. vid45 register, bit function description s bits bit name access description [6:4] vid5 r/w these bits set the output voltage for channel 5. 000 = 5. 00 v. 001 = 4.30 v. 010 = 4.25 v. 011 = 3.30 v. 100 = 3.20 v. 101 = 3.15 v. 110 = 3.10 v. 111 = 3.00 v. [2:0] vid4 r/w these bits set the output voltage for channel 4. 000 = 3.55 v. 001 = 3.30 v. 010 = 3.20 v. 011 = 3. 15 v. 100 = 3. 10 v. 101 = 2.80 v . 110 = 1.80 v. 111 = adjustable mode. register 15: vid6 ( output voltage for channel 6 ) , address 0x0 f r egister 15 sets the output voltage for channel 6 . t he default value i s defined by the fuse option. table 44. register 15 bit as signments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vid6 table 45. vid6 register, bit function description s bits bit name access description [3:0] vid6 r/w these bits set the output voltage for channel 6. 0000 = 5.5 v . 0001 = 5.4 v . 0010 = 5.3 v . 0011 = 5.2 v . 0100 = 5.15 v . 0101 = 5.1 v . 0110 = 5 .0 v . 0111 = 4.9 v . 1000 = 4.8 v . 1001 = 4.7 v . 1010 = 4.6 v . 1011 = 4.5 v . 110 0 = 4.4 v . 110 1 = 3.8 v . 111 0 = 3.5 v . 111 1 = a djustable m ode . rev. a | page 49 of 64
adp5080 data sheet register 16: vid7_ldo12 ( output voltage for channel 7, ldo1, and ldo2 ) , address 0x 10 r egister 16 sets the output voltage for channel 7, ldo1 , and ldo2 . t he default value s are defined by the fuse option. table 46. register 16 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vid_ldo2 vid_ldo1 vid7 table 47. vid7 _ldo12 register, bit function description s bits bit name access description [6:5] vid_ldo2 r/w these bits set the output voltage for ldo 2. 0 0 = 3.3 v . 0 1 = 3.2 v . 1 0 = 3.15 v . 1 1 = 3.0 v . 4 vid_ldo1 r/w these bits set the output voltage for ldo 1. 0 = 5.5 v . 1 = 5.0 v . [1:0] vid7 r/w these bits set the output voltage for channel 7. 00 = 12 v . 01 = 9 v . 10 = 6 v . 11 = 5 v. register 17: dvs 12 (dvs control for chann el 1 and channel 2 ) , address 0x 11 r egister 17 configures the dynamic voltage scaling (dvs) f unction for channel 1 and channel 2 . for more information, see the dynamic voltage scaling (dvs) function section. table 48. register 17 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dvs2_intval dvs1_intval en_dvs2 en_dvs1 table 49. dvs12 register, bit function description s bits bit name access description 5 dvs2_intva l r/w th is bit configure s the dvs interval for channel 2. 0 = 32 s ( d efault) . 1 = 64 s . 4 dvs1_intval r/w this bit configures the dvs interval for channel 1. 0 = 16 s ( d efault) . 1 = 32 s . 1 en_dvs2 r/w this bit enables or disables the dvs function fo r channel 2. 0 = disable dvs function for channel 2 (default) . 1 = enable dvs function for channel 2. 0 en_dvs1 r/w this bit enables or disables the dvs function for channel 1. 0 = disable dvs function for channel 1 (default) . 1 = enable dvs function for channel 1. rev. a | page 50 of 64
data sheet adp5080 register 18: sel_freq (switching frequency for channel 1 to channel 6 ) , address 0x 12 r egister 18 sets the master switching frequency (f sw ) and the switching frequency for each channel. t he default values are defined by the fuse option. ta ble 50. register 18 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sel_fsw freq6 freq5 freq4 freq3 freq2 freq1 table 51. sel_freq register, bit function description s bits bit name access description 7 se l_fsw r/w this bit selects the master switching frequency (f sw ). 0 = f sw is 2 mhz. 1 = f sw is 1.5 mhz. 5 freq6 r/w this bit sets the switching frequency for channel 6. 0 = 1 f sw . 1 = 1/2 f sw . 4 freq5 r/w this bit sets the switching f requency for channel 5. 0 = 1 f sw . 1 = 1/2 f sw . 3 freq4 r/w this bit sets the switching frequency for channel 4. 0 = 1 f sw . 1 = 1/2 f sw . 2 freq3 r/w this bit sets the switching frequency for channel 3. 0 = 1 f sw . 1 = 1/2 f sw . 1 freq2 r/w thi s bit sets the switching frequency for channel 2. 0 = 1 f sw . 1 = 1/2 f sw . 0 freq1 r/w this bit sets the switching frequency for channel 1. 0 = 1 f sw . 1 = 1/2 f sw . register 19: sel_freq _cp ( charge pump frequency) , address 0x 13 r egister 19 sets th e switching frequency for the charge pump and configures the clko output . the switching frequency for the charge pump depends on whether the device is synchronized to the internal clock or to an external clock. t he default value s are defined by the fuse op tion. table 52. register 19 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 en_clk o freq_cp table 53. sel_freq_cp register, bit function description s bits bit name access description 4 en_clko r/w this bit configures the clock output (clko) pin. the clko pin can output the internal switching clock used for channel 1 when the device is configured to use the internal oscillator . 0 = no output from clko pin. 1 = output from clko pin. [ 1:0] freq_cp r/w these bits set the charge pump switching frequency . bits[1:0] internal clock external clock 00 1/2 f sw 1/4 f sw 01 1/4 f sw 1/8 f sw 10 1/8 f sw 1/4 f sw 11 1/16 f sw 1/8 f sw rev. a | page 51 of 64
adp5080 data sheet register 20: sel_ phase (switching phase for channel 1 to channel 6 ) , address 0x 14 r egister 20 is used to reverse the phase of the switching clock to spread switching energy over time. t he default values for channel 2 to channel 6 are defined by the fuse option. table 54. register 20 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 phase6 phase5 phase4 phase3 phase2 phase1 table 55. sel_phase register, bit function description s bits bit name access description 5 phase6 r/w this bit sets the phase for channel 6. 0 = switching pulse in phase. 1 = switching pulse reversed. 4 phase5 r/w this bit sets the phase for channel 5. 0 = switching pulse in phase. 1 = switching pulse reversed. 3 phase4 r/w this bit sets the phase for ch annel 4. 0 = switching pulse in phase. 1 = switching pulse reversed. 2 phase3 r/w this bit sets the phase for channel 3. 0 = switching pulse in phase. 1 = switching pulse reversed. 1 phase2 r/w this bit sets the phase for channel 2. 0 = switching pulse i n phase. 1 = switching pulse reversed. 0 phase1 r/w this bit sets the phase for channel 1. 0 = switching pulse in phase (default) . 1 = switching pulse reversed. register 23: prot_dly (undervoltage/overvoltage protection delay time s ) , address 0x 17 r egist er 23 set s the delay time s to start under voltage and overvoltage protection. t he default values are defined by the fuse option. table 56. register 23 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 uv_dly ov_dly table 57. prot_dly register, bit function description s bits bit name access description [ 5:4] uv_dly r/w undervoltage protection delay time. 00 = 0 ms . 01 = 2 1 ms . 10 = 4 5 ms . 11 = disable undervoltage protection. [1:0] ov_dly r/w overvoltage protection delay time. 00 = 0 ms . 01 = 1.3 ms . 10 = 3.4 ms . 11 = disable overvoltage protection. rev. a | page 52 of 64
data sheet adp5080 register 24: pwrg ( power - good status ) , address 0x 18 r egister 24 is the read - only register for th e power - good status of channel 1 to channel 7 . a value of 1 for any pwrgx bit indicates that the power for that channel is good. t he en signal logic level can be monitored using bit 7 of this register. table 58. register 24 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 en pwrg7 pwrg6 pwrg5 pwrg4 pwrg3 pwrg2 pwrg1 table 59. pwrg register, bit function description s bits bit name access description 7 en r this bit displays the state of the en pin. 0 = en pin low (default). 1 = en pin high . 6 pwrg7 r this bit displays the power - good status of channel 7. 0 = power - good status low (default) . 1 = power - good status high . 5 pwrg6 r this bit displays the power - good status of channel 6. 0 = power - good status low (default) . 1 = power - good st atus high . 4 pwrg5 r this bit displays the power - good status of channel 5. 0 = power - good status low (default) . 1 = power - good status high . 3 pwrg4 r this bit displays the power - good status of channel 4. 0 = power - good status low (default) . 1 = power - good status high . 2 pwrg3 r this bit displays the power - good status of channel 3. 0 = power - good status low (default) . 1 = power - good status high . 1 pwrg2 r this bit displays the power - good status of channel 2. 0 = power - good status low (default) . 1 = power - good status high . 0 pwrg1 r this bit displays the power - good status of channel 1. 0 = power - good status low (default) . 1 = power - good status high . rev. a | page 53 of 64
adp5080 data sheet register 25: mask_pwrg ( power - good masked channel s ) , address 0x 19 r egister 25 masks and unm asks the power - good status for channel 1 to channel 7 . t he default values are defined by the fuse option. table 60. register 25 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mask_pwrg7 mask_pwrg6 mask_pwrg5 mask_ pwrg4 mask_pwrg3 mask_pwrg2 mask_pwrg1 table 61. mask_pwrg register, bit function description s bits bit name access description 6 mask_pwrg7 r/w this bit masks or unmasks the power - good status of channel 7. 0 = output power - good status of channel 7 to the fault pin . 1 = mask power - good status of channel 7 . 5 mask_pwrg6 r/w this bit masks or unmasks the power - good status of channel 6. 0 = output power - good status of channel 6 to the fault pin. 1 = mask power - good status of channel 6. 4 mask_pwrg5 r/w this bit masks or unmasks the power - good status of channel 5. 0 = output power - good status of channel 5 to the fault pin. 1 = mask power - good status of channel 5. 3 mask_pwrg4 r/w this bit masks or unmasks the power - good status of channel 4. 0 = output power - good status of channel 4 to the fault pin. 1 = mask power - good status of channel 4. 2 mask_ pwrg3 r/w this bit masks or unmasks the power - good status of chann el 3. 0 = output power - good status of channel 3 to the fault pin. 1 = mask power - good status of channel 3. 1 mask_pwrg2 r/w this bit masks or unmasks the power - good status of channel 2. 0 = output power - good status of channel 2 to the fault pin. 1 = mask power - good status of channel 2. 0 mask_pwrg1 r/w this bit masks or unmasks the power - good status of channel 1. 0 = output power - good status of channel 1 to the fault pin. 1 = mask power - good status of channel 1. register 26: uvpst ( underv oltage protection status ) , address 0x 1a register 26 indicate s the status of the undervoltage protection on channel 1 to channel 7. to clear any bit in this register, write a 1 to the bit. table 62. register 26 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 uv7 uv6 uv5 uv4 uv3 uv2 uv1 table 63. uvpst register, bit function description s bits bit name access description 6 uv7 read/ self - clear 0 = no und er voltage condition detected on channel 7 (default) . 1 = under voltage condition detected on channel 7. 5 uv6 read/ self - clear 0 = no under voltage condition detected on channel 6 (default) . 1 = under voltage condition detected on channel 6. 4 uv 5 read/ sel f - clear 0 = no under voltage condition detected on channel 5 (default) . 1 = under voltage condition detected on channel 5. 3 uv 4 read/ self - clear 0 = no under voltage condition detected on channel 4 (default) . 1 = under voltage condition detected on channel 4. 2 uv 3 read/ self - clear 0 = no under voltage condition detected on channel 3 (default) . 1 = under voltage condition detected on channel 3. 1 uv 2 read/ self - clear 0 = no under voltage condition detected on channel 2 (default) . 1 = under voltage condition det ected on channel 2. 0 uv 1 read/ self - clear 0 = no under voltage condition detected on channel 1 (default) . 1 = under voltage condition detected on channel 1. rev. a | page 54 of 64
data sheet adp5080 register 27: ovpst ( overv oltage protection status ) , address 0x 1b register 27 indicate s the status of the ov ervoltage protection on channel 1 to channel 6 . to clear any bit in this register, write a 1 to the bit. table 64. register 27 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ov6 ov5 ov4 ov3 ov2 ov1 ta ble 65. ovpst register, bit function description s bits bit name access description 5 ov6 read/ self - clear 0 = no over voltage condition detected on channel 6 (default) . 1 = over voltage condition detected on channel 6. 4 ov 5 read/ s elf - clear 0 = no over voltage condition detected on channel 5 (default) . 1 = over voltage condition detected on channel 5. 3 ov 4 read/ self - clear 0 = no over voltage condition detected on channel 4 (default) . 1 = over voltage condition detected on channel 4. 2 ov 3 read/ self - clear 0 = no over voltage condition detected on channel 3 (default) . 1 = over voltage condition detected on channel 3. 1 ov 2 read/ self - clear 0 = no over voltage condition detected on channel 2 (default) . 1 = over voltage condition detected on channel 2. 0 o v 1 read/ self - clear 0 = no over voltage condition detected on channel 1 (default) . 1 = over voltage condition detected on channel 1. register 28: a uto - psm ( auto psm or force d pwm mode for channel 1 to channel 6 ) , address 0x 1c r egister 28 configures channel 1 to channel 6 for either forced pwm operation or auto matic pwm/ psm operation. t he default values are defined by the fuse option. table 66. register 28 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 auto - psm6 auto - psm5 auto - psm4 auto - psm3 auto - psm2 auto - psm1 table 67. auto - psm register, bit function description s bits bit name access description 5 auto - psm6 r/w 0 = enable forced pwm mode for channel 6. 1 = enable automa tic pwm/psm mode for channel 6. 4 auto - psm5 r/w 0 = enable forced pwm mode for channel 5. 1 = enable automatic pwm/psm mode for channel 5. 3 auto - psm4 r/w 0 = enable forced pwm mode for channel 4. 1 = enable automatic pwm/psm mode for channel 4. 2 auto - psm3 r/w 0 = enable forced pwm mode for channel 3. 1 = enable automatic pwm/psm mode for channel 3. 1 auto - psm2 r/w 0 = enable forced pwm mode for channel 2. 1 = enable automatic pwm/psm mode for channel 2. 0 auto - psm1 r/w 0 = enable forced pwm mode for channel 1. 1 = enable automatic pwm/psm mode for channel 1. rev. a | page 55 of 64
adp5080 data sheet register 29: seq_mode (sequencer mode), address 0x 1d r egister 29 selects the power - up/power - down control mode for channel 1 to channel 7 : i 2 c control (manual) mode or sequence r mode (for mo re information, see the e nabling and d isabling the output c hannels section) . t he default values are defined by the fuse option. table 68. register 29 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mode_en7 mode_en6 mode_en5 mode_en4 mode_en3 mode_en2 mode_en1 table 69. seq_mode register, bit function descriptions bits bit name access description 6 mode_en7 r/w this bit sets the power - up/power - down control mode for channel 7. 0 = i 2 c control mode. 1 = sequencer mode . 5 mode_en6 r/w this bit sets the power - up/power - down control mode for channel 6. 0 = i 2 c control mode. 1 = sequencer mode. 4 mode_en5 r/w this bit sets the power - up/power - down control mode for chann el 5. 0 = i 2 c control mode. 1 = sequencer mode. 3 mode_en4 r/w this bit sets the power - up/power - down control mode for channel 4. 0 = i 2 c control mode. 1 = sequencer mode. 2 mode_en3 r/w this bit sets the power - up/power - down control mode for channel 3. 0 = i 2 c control mode. 1 = sequencer mode. 1 mode_en2 r/w this bit sets the power - up/power - down control mode for channel 2. 0 = i 2 c control mode. 1 = sequencer mode. 0 mode_en1 r/w this bit sets the power - up/power - down control mode for channel 1. 0 = i 2 c co ntrol mode. 1 = sequencer mode. register 30: adj_bst_vth 6 (adjust boost kick - in threshold and regulation mode for channel 6 ) , address 0x 1e r egister 30 sets the regulation mode for channel 6 ( b uck boost or b uck only) and adjust s the threshold of the boost regulator kick - in point when channel 6 is configured for buck boost regulation mode (for more information, see the channel 6: buck or buck b oost regulator section) . the default values are defined by the fuse option. table 70. register 30 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 buck6_only boost6_vth table 71. adj _ bst_vth6 register, bit function descriptions bits bit name access description 4 buck6_only r/w this bit sets the regulation mode for channel 6. 0 = buck boost mode. 1 = buck regulation only mode. [1:0] boost6_vth r/w these bits set the input threshold voltage for the boost fets . 00 = vout6/0.82 . 01 = vout6/0. 79. 10 = vout6/0. 77. 11 = vout6/0.8 5. rev. a | page 56 of 64
data sheet adp5080 register 31: opt _ sr _adj ( slew rate adjustment for channel 1 to channel 6 ) , address 0x 1f r egister 31 slows the switching slew rate of the specified channel , which reduces high frequency switching noise. the default value is 0 for all channels . table 72. register 31 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adj_sr6 adj_sr5 adj_sr4 adj_sr3 adj_sr2 adj_sr1 table 73. opt _sr _ adj register, bit function descriptions bits bit name access description 5 adj_sr6 r/w this bit sets the slew rate for channel 6. 0 = normal slew rate (default) . 1 = reduced slew rate. 4 adj_sr5 r/w this bit sets the slew rate for channel 5. 0 = normal slew rate (default) . 1 = reduced slew rate. 3 adj_sr4 r/w th is bit sets the slew rate for channel 4. 0 = normal slew rate (default) . 1 = reduced slew rate. 2 adj_sr3 r/w this bit sets the slew rate for channel 3. 0 = normal slew rate (default) . 1 = reduced slew rate. 1 adj_sr2 r/w this bit sets the slew rate for channel 2. 0 = normal slew rate (default) . 1 = reduced slew rate. 0 adj_sr1 r/w this bit sets the slew rate for channel 1. 0 = normal slew rate (default) . 1 = reduced slew rate. register 32: dcm56_gscal1 (auto dcm for channel 5 and channel 6, gate scali ng for channel 1 ) , address 0x 20 r egister 32 is used to enable or disable auto matic dcm mode on channel 5 and channel 6 . r egister 32 is also used to set the gate size for channel 1 : either full or half size (for more information, see the gate scaling (channel 1 o nly) section) . the default values are defined by the fuse option. table 74. register 32 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dcm56 gate _ scal1 table 75. dcm56_gscal1 register, bit function descriptions bits bit name access description 4 dcm56 r/w this bit sets the operational mode for channel 5 and channel 6. this bit can be set to 1 only when the a uto - psm 6 and a uto - psm 5 bits in register 28 ar e set to 1. 0 = enable automatic pwm/psm operation for channel 5 and channel 6. 1 = enable automatic dcm operation for channel 5 and channel 6. 0 gate_scal1 r/w t his bit enables or disables the gate scaling f unction for channel 1. 0 = disable gate scaling on channel 1 . 1 = enable gate scaling on channel 1 (gate size is halved). rev. a | page 57 of 64
adp5080 data sheet register 33: sel_inp_ldo12 (input selection for ldo1 and ldo2 ) , address 0x 21 r egister 33 is used to set the input path for ldo1 and ldo2 . the default values are defined by the fuse option. table 76. register 33 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sel_inp_ldo2 sel_inp_ldo1 table 77. sel _ inp_ldo12 register, bit function descriptions bits bit name access description 4 sel_inp_ldo2 r/w this bit sets the input path for ldo 2. 0 = vreg1 . 1 = visw2. 0 sel_inp_ldo1 r/w this bit sets the input path for ldo 1. 0 = vbat t . 1 = visw1. register 34: sel_ind_uv5 ( independent uvp control for channel 5 ) , addres s 0x 22 r egister 34 configures independent uvp control for channel 5. w hen b it 0 is set to 1, uvp control on channel 5 operates independent ly of uvp control on the other channels , and the uv_dly 5 bit s can be used to set a delay time separate from the uv_dly setting in register 23. the default values are defined by the fuse option. table 78. register 34 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 uv_dly5 sel_ind_uv5 table 79. sel_ind_ uv5 register, bit function descriptions bits bit name access description [ 5:4] uv_dly5 r/w undervoltage protection delay time for channel 5. these bits are valid only when sel_in d _ uv 5 = 1 . 00 = 0 ms . 01 = 2 1 ms . 10 = 4 5 ms . 11 = disable standalone undervo ltage protection on channel 5. 0 sel_in d _uv 5 r/w this bit enables or disables standalone uvp control for channel 5. 0 = uvp control for channel 5 synchronized with uvp control of other channels. 1 = s tandalone uvp control for channel 5. rev. a | page 58 of 64
data sheet adp5080 reg ister 35: option_sel (c hannel 1 output voltage reduction, disable delay time increase, en34 f unction ), address 0x 23 register 35 is used to set the following options: ch annel 1 output voltage range, global disable delay time range, and independent e nable fu nction for c hannel 3 and c hannel 4 via the en34 pin. the default values are defined by the fuse option. table 80. register 35 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reduce_vout1 dis_dly_extend dis_en34_ ch4 dis_en34_ch3 table 81. option_ sel register, bit function descriptions bits bit name access description 3 reduce_vout 1 r/w this bit sets the output voltage range for channel 1 (see tabl e 39 ) . 0 = normal output range . 1 = reduced output range . 2 dis_dly_extend r/w this bit sets the disable delay time (see table 31 , table 33, table 35 , and table 37) . 0 = normal disable delay time . 1 = extended disable delay time ( 4 the normal time). 1 dis_en34_ch4 r/w this bit specifies whether the en34 pin controls the enabling and disabling of channel 4. 0 = en34 pin controls channel 4. 1 = en 34 pin does not control channel 4 . 0 dis_en34_ch3 r/w this bit specifies whether the en 34 pin controls the enabling and disabling of channel 3. 0 = en 34 pin controls channel 3 . 1 = en 34 pin does not control channel 3. rev. a | page 59 of 64
adp5080 data sheet register 48: pctrl (c hannel enable control), address 0x 30 register 48 enables and disables the operation of individual channels (channel 1 to channel 7 ). this register is reset when the en pin is taken low or when an internal power - on reset occurs . all channels that are not configured for s equencer m ode in register 29 (address 0x1d) can be manually turned on and off using the ch x _on bits in the pctrl register. writing 1 to the ch x _on bit takes effect only when the en pin is logic high. when the en pin is logic low, all chann els configured for m anual m ode turn off immediately , and the appropriate ch x _on bits are reset. when the en pin is low, any data written to or read from the pctrl register is not valid. table 82. register 48 bit assignments bit 7 bi t 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rdst_pctrl ch7_on ch6_on ch 5 _on ch 4 _on ch 3 _on ch 2 _on ch 1 _on table 83. pctrl register, bit function descriptions bits bit name access description 7 rdst_pctrl r this bit indicates whether d ata is valid. repeat the read operation until this bit changes to 1. at least two read operations are require d before this bit changes to 1. 0 = data is not yet valid. 1 = data is valid. 6 ch7_on r /w this bit enables or disables channel 7. 0 = disable cha nnel 7 (default) . 1 = enable channel 7 . 5 ch6_on r /w this bit enables or disables channel 6. 0 = disable channel 6 (default) . 1 = enable channel 6. 4 ch5_on r/w this bit enables or disables channel 5. 0 = disable channel 5 (default) . 1 = enable channel 5 . 3 ch4_on r/w this bit enables or disables channel 4. this bit may be masked if the dis_en34_ch4 bit in register 35 is set to 0. 0 = disable channel 4 (default) . 1 = enable channel 4. 2 ch3_on r/w this bit enables or disables channel 3. this bit may be masked if the dis_en34_ch 3 bit in register 35 is set to 0. 0 = disable channel 3 (default) . 1 = enable channel 3. 1 ch2_on r/w this bit enables or disables channel 2. 0 = disable channel 2 (default) . 1 = enable channel 2. 0 ch1_on r/w this bit enables or disables channel 1. 0 = disable channel 1 (default) . 1 = enable channel 1. rev. a | page 60 of 64
data sheet adp5080 rev. a | page 61 of 64 factory default options table 84 lists the factory default options programmed into the adp5080 when the device is ordered (see the ordering guide). to order the device with options other than the default options, contact your local analog devices sales or distribution representative. for information about all available configuration options, see the control register details section. table 84. factory default fuse option settings register register addr (hex) register name bit bit name default setting binary code description 1 0x01 dscg 6 dscg7_on on 1 channel 7 output discharge 5 dscg6_on on 1 channel 6 output discharge 4 dscg5_on on 1 channel 5 output discharge 3 dscg4_on on 1 channel 4 output discharge 2 dscg3_on on 1 channel 3 output discharge 1 dscg2_on on 1 channel 2 output discharge 0 dscg1_on on 1 channel 1 output discharge 2 0x02 sfttim1234 [7:6] ss4 8 ms 11 channel 4 soft start time [5:4] ss3 1 ms 00 channel 3 soft start time [3:2] ss2 1 ms 00 channel 2 soft start time [1:0] ss1 1 ms 00 channel 1 soft start time 3 0x03 sfttim567 4 ss7 2 ms 0 channel 7 soft start time [3:2] ss6 2 ms 01 channel 6 soft start time [1:0] ss5 8 ms 11 channel 5 soft start time 4 0x04 en_dly12 [6:4] en_dly2 2 ms 001 channel 2 enable delay time [2:0] en_dly1 0 ms 000 channel 1 enable delay time 5 0x05 en_dly34 [6:4] en_dly4 0 ms 000 channel 4 enable delay time [2:0] en_dly3 0 ms 000 channel 3 enable delay time 6 0x06 en_dly56 [6:4] en_dly6 4 ms 010 channel 6 enable delay time [2:0] en_dly5 4 ms 010 channel 5 enable delay time 7 0x07 en_dly7 [2:0] en_dly7 6 ms 011 channel 7 enable delay time 8 0x08 dis_dly12 [6:4] dis_dly2 0 ms 000 channel 2 disable delay time [2:0] dis_dly1 12 ms 011 channel 1 disable delay time 9 0x09 dis_dly34 [6:4] dis_dly4 0 ms 000 channel 4 disable delay time [2:0] dis_dly3 0 ms 000 channel 3 disable delay time 10 0x0a dis_dly56 [6:4] dis_dly6 0 ms 000 channel 6 disable delay time [2:0] dis_dly5 0 ms 000 channel 5 disable delay time 11 0x0b dis_dly7 [2:0] dis_dly7 0 ms 000 channel 7 disable delay time 12 0x0c vid1 [4:0] vid1 0.80 v 11111 channel 1 output voltage 13 0x0d vid23 [6:4] vid3 adjustable 111 channel 3 output voltage [3:0] vid2 1.8 v 0100 channel 2 output voltage 14 0x0e vid45 [6:4] vid5 3.3 v 011 channel 5 output voltage [2:0] vid4 adjustable 111 channel 4 output voltage 15 0x0f vid6 [3:0] vid6 adjustable 1111 channel 6 output voltage 16 0x10 vid7_ldo12 [6:5] vid_ldo2 3.3 v 00 ldo2 output voltage 4 vid_ldo1 5.0 v 1 ldo1 output voltage [1:0] vid7 5.0 v 11 channel 7 output voltage 18 0x12 sel_freq 7 sel_fsw 2 mhz 0 master clock frequency 5 freq6 1/2 f sw 1 channel 6 switching frequency 4 freq5 1/2 f sw 1 channel 5 switching frequency 3 freq4 1/2 f sw 1 channel 4 switching frequency 2 freq3 1/2 f sw 1 channel 3 switching frequency 1 freq2 1/2 f sw 1 channel 2 switching frequency 0 freq1 1/2 f sw 1 channel 1 switching frequency
adp5080 data sheet register register addr ( h ex) register name bit bit name defa ult setting binary code de scription 19 0x 13 sel_freq_cp 4 en_clko e nabled 1 enable c lock o utput [1:0] freq_cp 1/4 f sw 01 charge p ump f requency 20 0x 14 sel_phase 5 phase6 reverse d 1 ch annel 6 s witching p hase 4 phase5 in p hase 0 ch annel 5 s witching p hase 3 phase4 reverse d 1 ch annel 4 s witching p hase 2 pha se3 in p hase 0 ch annel 3 s witching p hase 1 phase2 reverse d 1 ch annel 2 s witching p hase 23 0x 17 prot_dly [ 5:4] uv_dly 21 ms 01 undervoltage d elay t ime [1:0] ov_dly 1.3 ms 01 overvoltage d elay t ime 25 0x 19 mask_pwrg 6 mask_pwrg7 masked 1 ch annel 7 p ower -g ood m ask 5 mask_pwrg6 not m asked 0 ch annel 6 p ower -g ood m ask 4 mask_pwrg5 masked 1 ch annel 5 p ower - g ood m ask 3 mask_pwrg4 not m asked 0 ch annel 4 p ower -g ood m ask 2 mask_pwrg3 not m asked 0 ch annel 3 p ower -g ood m ask 1 mask_pwrg2 not m asked 0 ch annel 2 p ower -g ood m ask 0 mask_pwrg1 not m asked 0 ch annel 1 p ower -g ood m ask 28 0x 1c auto - psm 5 auto - psm6 a uto psm 1 ch annel 6 a uto psm e nable 4 auto - psm5 a uto psm 1 ch annel 5 a uto psm e nable 3 auto - psm4 a uto psm 1 ch annel 4 a uto ps m e nable 2 auto - psm3 a uto psm 1 ch annel 3 a uto psm e nable 1 auto - psm2 a uto psm 1 ch annel 2 a uto psm e nable 0 auto - psm1 a uto psm 1 ch annel 1 a uto psm e nable 29 0 x 1 d seq_mode 6 mode_en7 i 2 c m ode 0 ch annel 7 s equencer e nable 5 mode_en6 sequen cer m ode 1 ch annel 6 s equencer e nable 4 mode_en5 i 2 c m ode 0 ch annel 5 s equencer e nable 3 mode_en4 sequencer m ode 1 ch annel 4 s equencer e nable 2 mode_en3 sequencer m ode 1 ch annel 3 s equencer e nable 1 mode_en2 sequencer m ode 1 ch annel 2 s eque ncer e nable 0 mode_en1 sequencer m ode 1 ch annel 1 s equencer e nable 30 0x 1e adj_bst_vth6 4 buck6_only buck b oost 0 ch annel 6 b uck or b uck b oost [1:0] boost6_vth v out 6/ 0.82 00 ch annel 6 b uck b oost t hreshold 32 0x 20 dcm 56 _gscal 1 4 dcm56 auto psm 0 ch annel 5/ ch annel 6 e nable dcm m ode 0 gate_scal1 disabled 0 ch annel 1 e nable g ate s caling 33 0x 21 sel_inp_ldo12 4 sel_inp_ldo2 visw 2 1 ldo2 i nput s elect 0 sel_inp_ldo1 visw 1 1 ldo1 i nput s elect 34 0x 22 sel_ind_uv5 [ 5:4] uv_dly5 45 ms 10 ch annel 5 uvp d elay t ime 0 sel_in d _uv 5 sync with uvp 0 ch annel 5 i ndependent uvp control 35 0x 23 option_sel 3 reduce_vout 1 reduced vid 1 range 1 ch annel 1 o utput v oltage r ange 2 dis_dly_extend normal d isable d elay t ime 0 extend d isable d elay t ime 1 dis_ en34_ch4 en 34 control 0 ch annel 4 enable c ontrol via en 34 0 dis_en34_ch3 en 34 control 0 ch annel 3 enable c ontrol via en34 rev. a | page 62 of 64
data sheet adp5080 outline dimensions figure 60 . 72- ball wafer level chip scale package [wlcsp] ( cb - 72 -2) dimensions sh own in millimeters ordering guide model 1 temperature range package description package option adp5080a cbz -1-rl ?25 c to + 85c 72- ball wafer level chip scale package [wlcsp], 0.5 mm pitch cb-72-2 1 z = rohs compliant part. 07-31-2012- a a b c d e f g h 0.660 0.600 0.540 4.50 4.46 4.42 4.00 3.96 3.92 1 2 3 45 bot t om view (bal l side up) top view (bal l side down) side view 0.270 0.240 0.210 0.390 0.360 0.330 0.360 0.320 0.280 3.50 ref 4.00 ref 0.50 bal l pitch bal l a1 identifier 6789 coplanarity 0.05 sea ting plane rev. a | page 63 of 64
adp5080 data sheet notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors) . ? 2013 C 2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11639 - 0 - 4/14(a) rev. a | page 64 of 64

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